Method of forming self aligned contacts for a power mosfet

• US 20040058481A1
• Filed: 09/24/2002
• Published: 03/25/2004
• Est. Priority Date: 09/24/2002
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Korec, Jacek, Xu, Robert Q.
• Granted Patent: US 8,629,019 B2
• Time in Patent Office: Days
• US Class Current: 438/135
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for providing self aligned contacts for a trench power MOSFET is disclosed. The method includes, etching trenches in a substrate through a mask of silicon nitride deposited on an oxide layer, forming a gate oxide layer on the walls of the trenches, applying polysilicon to fill the trenches and to cover the surface of the mask of silicon nitride, removing the polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus. The method further includes recessing polysilicon plugs formed in trenches that are located in the active area to form recesses above the polysilicon plugs, filling recesses formed above the polysilicon plugs formed in trenches that are located in the active area with an insulator, applying a fourth photo resist mask to define contact windows that are opened in the nitride layer, and selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area. Moreover, electric contact trenches are defined using self-aligned spacer operations, and a fifth photo resist mask is applied to pattern metal contacts that reach the semiconductor device active areas.

Claims

1. A method for providing self aligned contacts in a semiconductor device arrangement comprising:

etching trenches in substrate through a photo resist mask of silicon nitride deposited on an oxide layer and forming a gate oxide layer on the walls of said trenches;

applying polysilicon to fill said trenches and to cover the surface of said mask of silicon nitride;

removing said polysilicon from the surface of the mask of silicon nitride and thereafter applying a photoresist mask to cover a location of a gate bus; and

recessing polysilicon plugs formed in trenches that are located in an active area to form recesses above the polysilicon plugs.

2. The method of claim 1, further comprising:

filling recesses formed above said polysilicon plugs, that are formed in said trenches located in said active area, with an insulator and applying a subsequent photo resist mask to define contact windows that are opened in the nitride layer;

selectively etching the silicon nitride film and leaving flat surfaced oxide buttons covering the trenches that are located in the active area and thereafter defining electric contact trenches for contacting active regions using self-aligned spacer operations; and

applying another photo resist mask to pattern metal contacts that reach the semiconductor device active areas.

3. The method of claim 2, further comprising isolating polysilicon material located in the active area of a semiconductor device and providing access to the top of a polysilicon plug located in a gate bus area of said semiconductor device.

4. The method of claim 3, wherein said removing said polysilicon from the surface of the mask of silicon nitride comprises a CMP (chemo mechanical polishing method) operation.

5. The method of claim 4, wherein said applying a photoresist mask distinguishes between the active area of said semiconductor device and the gate bus area.

6. The method of claim 5, wherein said polysilicon plugs have a height in the gate bus area that is coincident with the surface of the mask.

7. The method of claim 2, wherein said insulator is etched selectively with regard to the mask.

8. The method of claim 7, wherein said insulator comprises oxide or BPSG.

9. The method of claim 2, further comprising making electrical contact between the polysilicon plug and the metal that forms the gate bus.

10. The method of claim 3, wherein said etching trenches in a substrate comprises etching a wide trench.

11. The method of claim 10, wherein said wide trench is filled with a polycrystalline film having a semiconductor device that is integrated with a transistor formed in said active area formed therein.

12. The method of claim 2, further comprising:

creating oxide spacers along the walls of said contact windows;

etching the substrate surface to form a contact trench in the contact areas in a RIE operation; and

forming a contact implant at the bottom of said contact trench to increase the dopant concentration in a body well at the contact interface,

wherein the source regions are contacted along the side walls of said contact trench.

13. A method for providing self aligned contacts in an integrated MOSFET arrangement comprising:

providing a semiconductor substrate having a first surface and forming a plurality of semiconductor devices that are accessible at said first surface of said semiconductor substrate;

etching trenches in said substrate through a photo resist mask of silicon nitride deposited on an oxide layer and forming a gate oxide layer on the walls of said trenches;

applying polysilicon to fill said trenches and to cover the surface of said mask of silicon nitride; and

removing said polysilicon from the surface of the mask of silicon nitride and applying a photoresist mask to cover a location of a gate bus.

14. The method of claim 13, further comprising:

recessing polysilicon plugs formed in trenches that are located in an active area to form recesses above the polysilicon plugs and filling said recesses formed above said polysilicon plugs, that are formed in said trenches located in said active area, with an insulator;

applying a subsequent photo resist mask to define contact windows that are opened in the nitride layer and selectively etching the silicon nitride film to leave flat surfaced oxide buttons covering the trenches that are located in the active area; and

defining electric contact trenches for contacting active regions using self-aligned spacer operations and applying another photo resist mask to pattern metal contacts that reach the semiconductor device active areas.

15. The method of claim 14, further comprising isolating polysilicon material located in the active area of said integrated semiconductor device and providing access to the top of a polysilicon plug located in a gate bus area of said integrated semiconductor device.

16. The method of claim 15, wherein said removing said polysilicon from the surface of the mask of silicon nitride comprises a CMP (chemo mechanical polishing method) operation.

17. The method of claim 16, wherein said applying a photoresist mask distinguishes between the active area of the semiconductor device and the gate bus area.

18. The method of claim 17, wherein said polysilicon plugs have a height in the gate bus area that is coincident with the surface of the mask.

19. The method of claim 14, wherein said insulator is etched selectively with regard to the mask.

20. The method of claim 19, wherein said insulator comprises oxide or BPSG.

21. The method of claim 14, further comprising making electrical contact between the polysilicon plug and the metal that forms the gate bus.

22. The method of claim 15, wherein said etching trenches in a substrate comprises etching a wide trench.

23. The method of claim 22, wherein said wide trench is filled with a polycrystalline film having a semiconductor device that is integrated with a transistor formed in said active area.

24. The method of claim 14, further comprising:

creating oxide spacers along the walls of said contact windows;

etching the substrate surface to form a contact trench in the contact areas in a RIE operation; and

forming a contact implant at the bottom of said contact trench to increase the dopant concentration in a body well at the contact interface,

wherein the source regions are contacted along the side walls of said contact trench.

25. A method for providing self aligned contacts in an integrated MOSFET arrangement comprising:

providing a semiconductor substrate having a first surface and forming a plurality of semiconductor devices that are accessible at said first surface of said semiconductor substrate;

creating oxide spacers along the walls of contact windows formed in said substrate and etching the substrate surface to form a contact trench in the contact areas in a RIE operation; and

forming a contact implant at the bottom of said contact trench to increase the dopant concentration in a body well at the contact interface, wherein the source regions are contacted along the side walls of said contact trench.

26. The method of claim 25, further comprising isolating polysilicon material located in the active area of a semiconductor device and providing access to the top of a polysilicon plug located in a gate bus area of said semiconductor device.

27. The method of claim 26, further comprising removing said polysilicon material from the surface of a mask of silicon nitride in a CMP (chemo mechanical polishing method) operation.

28. The method of claim 27, further comprising applying a photoresist mask that distinguishes between the active area of said semiconductor device and the gate bus area of said device.

29. The method of claim 28, wherein said polysilicon plug has a height in the gate bus area that is coincident with the surface of the mask.

30. The method of claim 29, wherein an insulator is etched selectively with regard to said mask.

31. The method of claim 30, wherein said insulator comprises oxide or BPSG.

32. The method of claim 26, further comprising making electrical contact between said polysilicon plug and the metal that forms the gate bus.

33. The method of claim 32, further comprising etching a wide trench in said substrate.

34. The method of claim 33, wherein said wide trench is filled with a polycrystalline film that has a semiconductor device formed therein.