Data processing architecture

• US 20040059436A1
• Filed: 03/24/2003
• Published: 03/25/2004
• Est. Priority Date: 04/30/2001
• Status: Abandoned Application

• Current Assignee: Commonwealth of Australia
• Original Assignee: Commonwealth of Australia
• Inventors: Anderson, Mark Stephen, Randhawa, Suneel Singh, Engelhardt, Dean Crawford, Marriott, Damian Andrew
• Application Number:
  US10/312,807
• Publication Number:
  US 20040059436A1
• Time in Patent Office: Days
• US Class Current: 700/2
• CPC Class Codes: G06F 11/328 Computer systems status display G06F11/327 takes precedence
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling
• CPC Class Codes: G06F 11/3495 for systems
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06T 11/206 Drawing of charts or graphs
• CPC Class Codes: G06T 2200/24 involving graphical user interfaces [GUIs]
• CPC Class Codes: H04L 41/046 comprising network management agents or mobile agents therefor
• CPC Class Codes: H04L 41/0686 Additional information in the notification, e.g. enhancement of specific meta-data
• CPC Class Codes: H04L 41/22 comprising specially adapted graphical user interfaces [GUI]

Abstract

Data processing architecture comprises one or more data processing components associated with a logical level such that a data processing component associated with a logical level only accepts input from one or more data processing components in a logically higher or lower logical level or an external source; a data processing component associated with a logical level only provides output to one or more data processing components in a logically higher or lower level or an external recipient system. Each data processing component can not accept input or provide output from or to a data processing component in the same logical level; and a data processing component will only accept an input that conforms to an ontology related to the logical level with which the data processing component is associated.

Claims

1. Data processing architecture comprises

one or more data processing components associated with a logical level such that

a data processing component associated with a logical level only accepts input from one or more data processing components in a logically higher or lower logical level or an external source;

a data processing component associated with a logical level only provides output to one or more data processing components in a logically higher or lower level or an external recipient system;

wherein a data processing component can not accept input or provide output from or to a data processing component in the same logical level; and

a data processing component will only accept an input that conforms to an ontology related to the logical level with which the data processing component is associated.

2. Data processing architecture according to claim 1 wherein a said input received by a data processing component is context-free with respect to said ontology.

3. Data processing architecture according to claim 1 wherein the input received by a data processing component has a temporal context and the data processing component performs filtering based on the temporal context.

4. Data processing architecture according to claim 1 further comprises one or more stores wherein statements in an ontology that can be outputs from a data processing component or from an external source in the same ontology are associated with a respective store.

5. Data processing architecture according to claim 4 wherein a said external source of input to a data processing component is a store.

6. Data processing architecture according to claim 4 wherein the output of a data processing component to be stored is a subset of the outputs of said data processing component.

7. Data processing architecture according to claim 6 wherein a human determines the subset of the output.

8. Data processing architecture according to claim 1 wherein a data processing component has a memory state that may contain input, output or any knowledge statement derived from input.

10. Data processing architecture according to claim 4 wherein a human determines a subset of a store for review of said subset of zero or more statements.

11. Data processing architecture according to claims 9 or 10 wherein said determination is an expression in a language.

12. Data processing architecture according to claim 11 wherein said language is natural or based on the ontology that is related to a respective data processing component or store.

13. Data processing architecture according to claims 11 or 12 wherein said expression is the result of the physical action of said human.

14. Data processing architecture according to claim 13 wherein said action is one or more of a spoken language or language expressed in text.

15. Data processing architecture according to claims 4 or 8 wherein a human adds statements to a data processing component'"'"'s memory state or store respectively.

16. Data processing architecture according to claim 1 wherein a data processing component operates in a data-driven forward chaining method.

17. Data processing architecture according to claim 1 wherein a data processing component operates in a goal driven backward chaining method.

18. Data processing architecture according to claim 1 wherein a data processing component accepts inputs simultaneously from multiple data processing components or external sources or combinations thereof.

19. Data processing architecture according to claim 1 wherein said data processing components, stores and external sources are physically located geographically remote of one or more other data processing components, stores or sources.

20. Data processing architecture according to claim 1 wherein said inputs are expressed in an ontology that describes a communications network.

21. Data processing architecture according to claim 20 wherein said communications network is described in real time.

22. Data processing architecture according to claim 20 wherein said communications network is described in a prior state.

23. Data processing architecture according to claim 1 wherein said inputs are expressed in an ontology that describes the operating system of a computer device.

24. Data processing architecture according to claim 21 wherein said computer device is described in real time.

25. Data processing architecture according to claim 23 wherein said computer device is described in a prior state.

26. Data processing architecture according to claim 1 wherein a human determines the association of a data processing component with a logical level.

27. Data processing architecture according to claim 26 wherein a human may change the association at any time.

28. Data processing architecture according to claim 19 wherein a human determines the physical location of data processing components, stores or sources.

29. Data processing architecture according to claim 28 wherein a human may change the physical location of data processing components, stores or sources at any time.

30. Data processing architecture according to claim 3 wherein a human determines the filtering based on the temporal context.

31. Data processing architecture according to claim 3 wherein a human changes the filtering based on the temporal context at any time.

32. Data processing architecture according to claim 1 wherein a human determines a set of data processing components in a higher or lower logical level from which a data processing component receives input.

33. Data processing architecture according to claim 1 wherein a human determines a set of data processing components in a higher or lower logical level that a data processing component can provide output to.

34. Data processing architecture according to claim 1 wherein a human determines one or more sets of logical levels and further wherein a human determines the logical level of the data processing component in the highest logical level of a set and determines the logical level of the data processing components in the lowest logical level of a further set.

35. Data processing architecture according to claim 1 wherein a human determines one or more sets of logical levels and further wherein a human determines the logical level of the data processing component in the lowest logical level of a set and determines the logical level of the data processing components in the highest logical level of a further set.

36. Data processing architecture according to claim 1 wherein said ontology is derived from entities and relationships that are pair-wise orthogonal.

37. Data processing architecture according to claim 1 wherein said ontology is derived from mathematical set theory wherein the sets are determined by the application.

38. Data processing architecture according to claim 1 wherein said ontology is derived from the consistency and inconsistency of knowledge.

39. Data processing architecture according to claim 38 wherein a statement of consistency or inconsistency is made with respect to a knowledge base of theory.

40. Data processing architecture according to claim 1 wherein said ontology is derived from the probability of knowledge being correct.

41. Data processing architecture according to claim 1 wherein said ontology is derived from the possibility of knowledge being correct.

42. Data processing architecture according to claim 41 wherein possibilities are determined explicitly or by a conditional expression.

43. Data processing architecture according to claim 11 wherein said language is derived from ontology derived from the possibility of knowledge being correct.

44. Data processing architecture according to claim 43 wherein said language includes an expression that evaluates whether it is impossible for knowledge in a memory state or store to be correct otherwise said expression evaluates that that knowledge is possibly correct.

45. Data processing architecture according to claim 43 wherein said language includes an expression that evaluates whether knowledge in a memory state or store is explicitly determined to be possible and further that there is no other knowledge in said memory state or store that implies it is impossible that that knowledge is correct.

46. Data processing architecture according to claim 43 wherein said language includes an expression such that given knowledge said expression evaluates a set of knowledge which is considered in conjunction with knowledge in said memory state or store that would imply said given knowledge is correct.

47. Data processing architecture according to any one of claims 44, 45 or 46 wherein said expression includes a set of knowledge to be considered with knowledge in a said memory state or store when evaluating said expression.

48. Data processing architecture according to any one of claims 44, 45, 46 or 47 wherein said expression includes a negation operator such that evaluation of said negation is conducted as a possiblistic query.

49. Data processing architecture according to claim 41 wherein a data processing component provides output to one or more data processing components in a higher or lower level by pruning of unification trees.

50. Data processing architecture according to claim 49 wherein said pruning is human specified.

51. Data processing architecture according to claim 49 wherein said pruning is specified by a said data processing component.

52. Data processing architecture according to claim 41 wherein the output of a data processing component is represented as statements describing knowledge as being either correct, possibly correct or impossible.

53. Data processing architecture according to claim 1 wherein a data processing component represents input received as vectors and calculates by vector algebra a vector that is associated with one or more known regions in a respective vector space which denote deductions.

54. Data processing architecture according to claim 53 wherein said vector algebra is exclusively vector summation.

55. Data processing architecture according to claim 53 wherein a deduction is the result of an association by proximity with respect to said known regions is a respective vector space.

56. Data processing architecture according to claim 55 wherein a known point defines a said known region.

57. Data processing architecture according to claim 53 wherein axes of said vector space are defined from entities and relationships that are pair-wise orthogonal.

9. Data processing architecture according to 8 wherein a human determines a subset of a said memory state for review of said subset of zero or more statements.

58. Data processing architecture comprising

one or more data processing components that will only accept an input that conforms to an ontology derived from the possibility of knowledge being correct wherein said data processing component provides output to one or more other data processing components or an external recipient system by pruning of unification trees.

59. Data processing architecture according to claim 58 wherein said pruning is human specified.

60. Data processing architecture according to claim 58 wherein said pruning is specified by a said data processing component.

61. Data processing architecture comprising

one or more data processing components that will only accept an input that conforms to an ontology and represent input received as vectors and calculate by vector algebra a vector that is associated with one or more known regions in a respective vector space that denotes deductions, wherein said data processing components provide output to one or more other data processing components or an external recipient system.

62. Data processing architecture according to claim 61 wherein said vector algebra is exclusively vector summation.

63. Data processing architecture according to claim 61 wherein a deduction is the result of an association by proximity with respect to said known regions is a respective vector space.

64. Data processing architecture according to claim 61 wherein a known point defines a said known region.

65. Data processing architecture according to claim 61 wherein axes of said vector space are defined from entities and relationships that are pair-wise orthogonal.