Method and apparatus for calibration of a delay element

• US 20040059533A1
• Filed: 09/25/2002
• Published: 03/25/2004
• Est. Priority Date: 09/25/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Mandal, Subrata, Parrish, Gregory C.
• Granted Patent: US 6,950,770 B2
• Time in Patent Office: Days
• US Class Current: 702/107
• CPC Class Codes: H03K 2005/00234 using circuits having two logic levels
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

Various methods, systems and apparatuses having an integrated circuit that contains a calibration circuit having a series of delay elements to receive a reference signal. The reference signal establishes a standard unit of time. The calibration circuit also generates one or more calibrated delay signals derived from the reference signal. The one or more calibrated delay signals are precise to a known fraction of the standard unit of time.

Claims

1. An integrated circuit, comprising:

a calibration circuit contained within the integrated circuit and having a series of delay elements to receive a reference signal, the reference signal is operable to establish a standard unit of time, wherein the calibration circuit also to generate one or more calibrated delay signals derived from the reference signal and precise to a known fraction of the standard unit of time.

2. The integrated circuit of claim 1, wherein the calibration circuit further comprises:

a sampling device; and

a multiplexer coupled to the sampling device, the multiplexer to selectively pass one or more of the calibrated delay signals to the sampling device to make a calibrated measurement of time referenced against at least one of the delay signals.

3. The integrated circuit of claim 2, wherein the calibrated measurement of time and the generation of the at least one calibrated delay signal occur at approximately at the same time.

4. The integrated circuit of claim 1, further comprising:

a sampling device coupled to receive an output signal from one of the delay elements in the series of delay elements as well as the reference signal.

5. The integrated circuit of claim 4, wherein the sampling device receives the calibrated delay signal from one of the delay elements in the series of delay elements through a multiplexer.

6. The integrated circuit of claim 1, wherein the calibration circuit to also generate a signal precise to within a known fraction of the standard unit of time and derived from the reference signal.

7. The integrated circuit of claim 1, wherein the series of delay elements includes a first delay element and a second delay element, the first delay element comprises a first matched pair of transistors and the second delay element comprises a second matched pair of transistors.

8. The integrated circuit of claim 1, wherein the series of delay elements includes a first delay element and a second delay element, the first delay element comprises a first buffer, the second delay element comprises a second buffer, and a standard unit of time comprises one or more clock pulses.

9. The integrated circuit of claim 1, wherein the calibration circuit has a given accuracy that is independent of the silicon process used to make the calibration circuit, operating voltage applied to the calibration circuit, or operating temperature to which the calibration circuit is exposed.

10. A computing system, comprising:

a clock circuit to generate a reference signal; and

an integrated circuit that contains a calibration circuit having a series of delay elements coupled to receive the reference signal, the reference signal is operable to establish a standard unit of time, wherein the calibration circuit also is operable to generate one or more calibrated delay signals derived from the reference signal and precise to a known fraction of the standard unit of time.

11. The computing system of claim 10, wherein the integrated circuit comprises a processor.

12. The computing system of claim 10, wherein the integrated circuit comprises a chip set.

13. The computing system of claim 10, further comprising:

a sampling device; and

a multiplexer coupled to the sampling device, the multiplexer to selectively pass one or more of the calibrated delay signals to the sampling device to make a calibrated measurement of time referenced against at least one of the delay signals.

14. The computing system of claim 13, wherein the calibrated measurement of time and the generation of the at least one calibrated delay signal occur at approximately at the same time.

15. The computing system of claim 10, wherein the calibration circuit to also generate a signal precise to within a known fraction of the standard unit of time and derived from the reference signal.

16. The computing system of claim 10, wherein each of the delay elements have substantially an equal delay time.

17. The computing system of claim 10, wherein each of the delay elements have unequal delay times but are fixed, repeatable, and have the same time delay relationship with respect to each other.

18. A method, comprising:

receiving a reference signal to establish a standard unit of time; and

generating a calibrated delay signal that is derived from the reference signal and that is also delayed from the reference signal by a known time value that is a fraction of the standard unit of time; and

making a timing measurement referenced against that calibrated delay signal.

19. The method of claim 18, further comprising:

making the timing measurement and generating the calibrated delay signal at approximately the same time.

20. The method of claim 18, further comprising:

determining a delay time of a single delay element by dividing the standard unit of time by the number of delay elements propagated thorough in one standard unit of time.

21. The method of claim 20, further comprising:

generating the known time value associated with the calibrated delay signal by combining the delay times of one or more delay elements.