Real time emulation of coherence directories using global sparse directories

• US 20040059876A1
• Filed: 09/25/2002
• Published: 03/25/2004
• Est. Priority Date: 09/25/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Sugavanam, Krishnan, Nanda, Ashwini
• Granted Patent: US 6,965,972 B2
• Time in Patent Office: Days
• US Class Current: 711/141
• CPC Class Codes: G06F 12/082 Associative directories G06F12/0822 takes precedence
• CPC Class Codes: G06F 9/45537 Provision of facilities of other operating environments, e.g. WINE I/O emulation G06F13/105

Abstract

A method and structure for an emulation system comprises of a plurality of field programmable gate arrays adapted to emulate nodes of a multi-node shared memory system, a plurality of cache directories, each connected to one of the arrays, and a plurality of global coherence directories, each connected to one of the arrays. Each of the global coherence directories maintain information on all memory lines remotely cached by each of the cache directories.

Claims

1. An emulation system comprising:

a plurality of field programmable gate arrays adapted to emulate nodes of a multi-node shared memory system;

a plurality of cache directories, each connected to one of said arrays; and

a plurality of global coherence directories each connected to one of said arrays, wherein each of said global coherence directories maintains information on all memory lines in all of said cache directories.

2. The system in claim 1, wherein said global coherence directories comprise sparse directories.

3. The system in claim 1, wherein each of said cache directories maintains information relating only to memory lines cached by a local array.

4. The system in claim 1, wherein said nodes comprise different computers in a multi-computer network.

5. The system in claim 1, wherein all of said global coherence directories of said multi-node shared memory system maintain identical information.

6. The system in claim 1, wherein by said global coherence directories maintaining information on all memory lines remotely cached by each of said cache directories, communication among said arrays is decreased and emulation efficiency is increased.

7. The system in claim 6, wherein emulation efficiency comprises a metric which is inversely proportional to pin utilization and area utilization of said arrays.

8. An emulation system for a network of computers comprising:

a plurality of field programmable gate arrays adapted to emulate computers in said network;

a plurality of cache directories, each connected to one of said arrays; and

a plurality of global coherence directories, each connected to one of said arrays, wherein each of said global coherence directories maintains information on all memory lines in all of said cache directories.

9. The system in claim 8, wherein said global coherence directories comprise sparse directories.

10. The system in claim 8, wherein each of said cache directories maintains information relating only to memory lines cached by a local array.

11. The system in claim 8, wherein all of said global coherence directories of said multi-node shared memory system maintain identical information.

12. The system in claim 8, wherein by said global coherence directories maintaining information on all memory lines remotely cached by each of said cache directories, communication among said arrays is decreased and emulation efficiency is increased.

13. The system in claim 12, wherein emulation efficiency comprises a metric which is inversely proportional to pin utilization and area utilization of said arrays.

14. A method of designing an emulation system comprising:

designing a plurality of field programmable gate arrays to emulate nodes of a multi-node shared memory system;

connecting a separate cache directory to each of said arrays; and

connecting a separate global coherence directory to each of said arrays, wherein each said global coherence directory maintains information on all memory lines in all cache directories.

15. The method in claim 14, wherein said designing of said arrays is performed such that each said cache directory maintains information relating only to memory lines cached by a local array to which said cache directory is connected.

16. The method in claim 14, wherein said designing of said arrays is performed such that all nodes of said multi-node shared memory system have a copy of coherence directories of all other nodes.

17. The method in claim 14, wherein all of said global coherence directories of said multi-node shared memory system maintain identical information.

18. The method in claim 14, wherein by said global coherence directories information on all memory lines remotely cached by each said cache directories, communication among said arrays is decreased and emulation efficiency is increased.

19. The method in claim 14, wherein emulation efficiency comprises a metric which is inversely proportional to pin utilization and area utilization of said arrays.

20. A program storage device readable by machine, tangibly embodying a program of instructions, executable by the machine to perform a method for designing an emulation system comprising:

designing a plurality of field programmable gate arrays to emulate nodes of a multi-node shared memory system;

connecting a separate cache directory to each of said arrays; and

connecting a separate global coherence directory to each of said arrays, wherein each said global coherence directory maintains information on all memory lines in all cache directories.

21. The program storage device in claim 20, wherein said designing of said arrays is performed such that each said cache directory maintains information relating only to memory lines cached by a local array to which said cache directory is connected.

22. The program storage device in claim 20, wherein said designing of said arrays is performed such that all nodes of said multi-node shared memory system have a copy of coherence directories of all other nodes.

23. The program storage device in claim 20, wherein all of said global coherence directories of said multi-node shared memory system maintain identical information.

24. The program storage device in claim 20, wherein by said global coherence directories information on all memory lines remotely cached by each said cache directories, communication among said arrays is decreased and emulation efficiency is increased.

25. The program storage device in claim 20, wherein emulation efficiency comprises a metric which is inversely proportional to pin utilization and area utilization of said arrays.