Device under test interface card with on-board testing

• US 20040059971A1
• Filed: 09/23/2002
• Published: 03/25/2004
• Est. Priority Date: 09/23/2002
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Cowan, Joseph W.
• Granted Patent: US 6,747,473 B2
• Time in Patent Office: Days
• US Class Current: 714/724
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736

Abstract

The present invention concerns an apparatus comprising a first plurality of contacts, a second plurality of contacts, one or more sockets, and a programmable processor. The first plurality of contacts may be configured to receive one or more first signals. The second plurality of contacts may be configured to present one or more second signals in response to the one or more first signals. The one or more sockets may be configured to receive one or more third signals from one or more programmable devices. The programmable processor may be configured to generate a test signal in response to (i) the one or more first signals and (ii) the one or more third signals.

Claims

1. An apparatus comprising:

a first plurality of contacts configured to receive one or more first signals;

a second plurality of contacts configured to present one or more second signals in response to said one or more first signals;

one or more sockets configured to receive one or more third signals from one or more programmable devices; and

a programmable processor configured to generate a test signal in response to (i) said one or more first signals and (ii) said one or more third signals.

2. The apparatus according to claim 1, wherein said test signal comprises a test sequence for a device under test.

3. The apparatus according to claim 2, wherein said device under test comprises a wafer or a packaged integrated circuit.

4. The apparatus according to claim 1, wherein said programmable devices comprise a memory.

5. The apparatus according to claim 1, wherein said programmable devices comprise a processor.

6. The apparatus according to claim 1, wherein said first plurality of contacts comprises connectors that connect to an interface assembly connected to an automatic test equipment.

7. The apparatus according to claim 1, wherein said second plurality of contacts comprises a collection of probe needles to connect to a device under test.

8. The apparatus according to claim 1, wherein said apparatus comprises an automatic test equipment interface card.

9. The apparatus according to claim 8, wherein said automatic test equipment interface card is implemented with a high speed, high pin count tester with scan capability in a failure analysis lab.

10. The apparatus according to claim 8, wherein said apparatus allows for at-speed, real-time testing of a device under test.

11. The apparatus according to claim 8, wherein said apparatus provides multiple setups to operate independently on different devices under test after being programmed by a single programmer without being connected to said programmer during test sequences.

12. The apparatus according to claim 2, wherein said test sequence comprises a failure analysis.

13. The apparatus according to claim 2, wherein said test sequence comprises a sequence configured to execute device analysis.

14. The apparatus according to claim 2, wherein said apparatus works in conjunction with a built-in self-test circuit on said device under test.

15. The apparatus according to claim 2, wherein said apparatus generates test signals with said programmable processor to be applied to the device under test.

16. An apparatus comprising:

means for receiving one or more first signals;

means for presenting one or more second signals in response to said one or more first signals;

means for receiving one or more third signals from one or more programmable devices; and

means for generating a test signal in response to (i) said one or more first signals and (ii) said one or more second signals.

17. A method of generating a test output for a device under test comprising the steps of:

(A) programming one or more programmable devices on a device under test interface card;

(B) interfacing between said device under test interface card and said device under test with a first plurality of contacts; and

(C) executing a program stored in said one or more programmable devices to generate said test output.

18. The method according to claim 17, further comprising the step of:

interfacing with a controller through a second plurality of contacts.

19. The method according to claim 17, wherein said one or more programmable devices comprise processors and memories.

20. The method according to claim 17, wherein said device under test comprises a wafer or a packed integrated circuit.