Time synthesis for power optimization of high performance circuits

• US 20040060016A1
• Filed: 09/22/2003
• Published: 03/25/2004
• Est. Priority Date: 09/28/2001
• Status: Abandoned Application

• Current Assignee: Barbara Chappell, Priyadarsan Patra
• Original Assignee: Barbara Chappell, Priyadarsan Patra
• Inventors: Chappell, Barbara, Patra, Priyadarsan
• Application Number:
  US10/665,521
• Publication Number:
  US 20040060016A1
• Time in Patent Office: Days
• US Class Current: 716/2
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/08 Thermal analysis or thermal optimisation
• CPC Class Codes: G06F 30/23 using finite element methods [FEM] or finite difference methods [FDM]

Abstract

A system and computer implemented method of modifying characteristics of a circuit provide enhanced performance. One embodiment of the method provides for determining a set of objective parameters for the circuit and receiving noise constraints for the circuit. Values of the objective parameters are optimized based on the noise constraints. By using noise constraints in the optimization process, a number of performance issues can be addressed.

Claims

1. A computer implemented method of modifying characteristics of a circuit, the method comprising:

determining a set of objective parameters for the circuit;

receiving noise constraints for the circuit; and

optimizing values of the objective parameters based on the noise constraints.

2. The method of claim 1 further including:

developing a set of sensitivity factors based on the objective parameters and noise margins in accordance with the noise constraints such that the sensitivity factors characterize a noise sensitivity of the circuit;

selecting objective parameter values and modified noise margins based on the sensitivity factors such that the objective parameter values minimize power costs to the circuit; and

repeating the developing and selecting until changes in the objective parameter values fall below a predetermined threshold.

3. The method of claim 2 further including:

allocating initial noise margins to a plurality of nodes in the circuit;

setting initial objective parameter values in accordance with the initial noise margins; and

repeating the allocating and setting for varied noise margins.

4. The method of claim 3 further including selecting discrete components of the objective parameters such that the objective parameter values define dynamic logic settings.

5. The method of claim 4 further including selecting one or more dynamic logic families, each dynamic logic family having dynamic gates with corresponding transistor widths and power levels.

6. The method of claim 3 further including selecting continuously tunable components of the objective parameters such that the objective parameter values define static logic settings.

7. The method of claim 6 further including selecting one or more static logic gates, each static logic gate having corresponding widths and power levels.

8. The method of claim 2 further including:

measuring power costs to a full cone of logic behind each node in the circuit;

calculating power costs to a full cone of logic ahead of each node in the circuit;

summarizing the measured and calculated power costs into a common sensitivity parameter.

9. The method of claim 2 further including:

constructing an objective function based on the sensitivity factors; and

inputting the objective function to a linear program solver such that the linear program solver generates the objective parameter values and the noise margins.

10. The method of claim 1 further including:

receiving timing constraints for the circuit; and

optimizing the objective parameter values based on the timing constraints.

11. The method of claim 10 further including:

determining timing margins in accordance with the timing constraints;

said timing margins including minimum and maximum delays for a plurality of nodes in the circuit.

12. The method of claim 1 further including:

receiving physical constraints for the circuit; and

optimizing the objective parameter values based on the physical constraints.

13. The method of claim 1 further including:

conducting a topological analysis on critical paths of the circuit, where the optimized objective parameter values are used in the critical paths;

correcting the objective parameters and noise constraints for topological costs that are above a predetermined level; and

repeating the optimizing with the corrected objective parameters and noise constraints.

14. The method of claim 13 further including splitting nets in the circuit.

15. The method of claim 13 further including merging nets in the circuit.

16. The method of claim 13 further including adding buffers to the circuit.

17. The method of claim 13 further including substituting cells in the circuit with library cells where the library cells have extended noise characteristics.

18. A computer implemented method of optimizing values of objective parameters for a circuit, the method comprising:

developing a set of sensitivity factors based on the objective parameters and noise margins in accordance with noise constraints for the circuit such that the sensitivity factors characterize a noise sensitivity of the circuit;

selecting objective parameter values and modified noise margins based on the sensitivity factors such that the objective parameter values minimize power costs to the circuit; and

repeating the developing and selecting until changes in the objective parameter values fall below a predetermined threshold.

19. The method of claim 18 further including:

allocating initial noise margins to a plurality of nodes in the circuit;

setting initial objective parameter values in accordance with the initial noise margins; and

repeating the allocating and setting for adjusted noise margins.

20. The method of claim 19 further including selecting discrete components of the objective parameters such that the objective parameter values define dynamic logic settings.

21. The method of claim 20 further including selecting one or more dynamic logic families, each dynamic logic family having dynamic gates with corresponding transistor widths and power levels.

22. The method of claim 19 further including selecting continuously tunable components of the objective parameters such that the objective parameter values define static logic settings.

23. The method of claim 22 further including selecting one or more static logic gates, each static logic gate having corresponding widths and power levels.

24. A computer-readable storage medium storing a set of instructions, the set of instructions capable of being executed by a processor to perform a method of optimizing values of objective parameters for a circuit, the method comprising:

developing a set of sensitivity factors based on the objective parameters and noise margins in accordance with noise constraints for the circuit such that the sensitivity factors characterize a noise sensitivity of the circuit;

selecting objective parameter values and modified noise margins based on the sensitivity factors such that the objective parameter values minimize power costs to the circuit; and

repeating the developing and selecting until changes in the objective parameter values fall below a predetermined threshold.

25. The medium of claim 24 wherein the method further includes:

allocating initial noise margins to a plurality of nodes in the circuit;

setting initial objective parameter values in accordance with the initial noise margins; and

repeating the allocating and setting for adjusted noise margins.

26. The medium of claim 25 wherein the method further includes selecting discrete components of the objective parameters such that the objective parameter values define dynamic logic settings.

27. The medium of claim 25 wherein the method further includes selecting continuously tunable components of the objective parameters such that the objective parameter values define static logic settings.