Electronic circuit device

• US 20040061147A1
• Filed: 07/15/2003
• Published: 04/01/2004
• Est. Priority Date: 01/19/2001
• Status: Active Grant

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Takahashi, Yasuhiko, Fujita, Ryo, Noguchi, Kouki, Kubo, Osamu, Kubo, Masaharu, Mishima, Michihiro
• Granted Patent: US 7,091,598 B2
• Time in Patent Office: Days
• US Class Current: 257/232
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

An electronic circuit device has a high-density mount board (2), on which are disposed a microcomputer (3) and random access memory (7) which are connected to each other through an exclusive memory bus (12) for high-speed data transfer, a programmable device (8) which is a variable logic circuit represented by FPGA, and an electrically-rewritable nonvolatile memory (16) which can store the operation program of the microcomputer. The high-density mount board has external mounting pins on the bottom surface so that it can be mounted on a mother board in the same manner as a system on-chip multi-chip module. With an intended logic function being set on the programmable device, a hardware-based function to be realized by the electronic circuit device can be simulated. With an operation program being written to the nonvolatile memory, a software-based function to be realized can be simulated. Consequently, the device facilitates the debugging at early stages of system development, configures a prototype system, and contributes to the time reduction throughout the system development, prototype fabrication and large-scale production.

Claims

1. An electronic circuit device comprising as semiconductor devices a microcomputer having CPU, a random access memory, and a programmable device which implements a logic function in a programmable manner in accordance with logic definition data loaded in numerous memory cells,

said microcomputer, random access memory and programmable device being formed on multiple semiconductor chips, which are mounted on one side of a common board different from said semiconductor chips,

said common board having on another side thereof external mounting pins for the connection to other circuit board,

said external mounting pins being adapted to connect to said programmable device.

2. An electronic circuit device according to claim 1, wherein said microcomputer includes a first electrically-rewritable nonvolatile memory which can store a CPU operation program.

3. An electronic circuit device according to claim 1, wherein said common board has a common bus for the connection between said microcomputer and said programmable device.

4. An electronic circuit device according to claim 1 further including a second electrically-rewritable nonvolatile memory which is mounted on said common board and connected to said common bus.

5. An electronic circuit device according to claim 1, wherein said microcomputer includes a memory buffer, which is connected to said random access memory through an exclusive memory bus, said exclusive memory bus being formed on said common board without being connected to said external mounting pins

6. An electronic circuit device according to claim 5, wherein said memory buffer has an output buffer which is connected to said exclusive memory bus, said output buffer including an output MOS transistor and an output impedance controlling MOS transistor which is coupled to said output MOS transistor, said output impedance controlling MOS transistor having its conduction impedance controlled by a control voltage which is put out from a control circuit.

7. An electronic circuit device according to claim 1, wherein said common board has a glass substrate and multi-wiring-layers which are formed on one main surface of said glass substrate, said multi-wiring-layers having on the surface thereof connection pins which are disposed to mount semiconductor devices and are conductive to certain wiring lines of said multi-wiring-layers, said glass substrate having on another main surface thereof said external mounting pins which are formed to penetrate said glass substrate and are conductive to certain wiring lines of said multi-wiring-layers.

8. An electronic circuit device comprising a plurality of semiconductor devices formed on separate semiconductor chips and mounted on one side of a build-up board which is common to said devices, said build-up board having on another side thereof external mounting pins for the connection to other circuit board,

said semiconductor devices having a plurality of scanning latches which are correspondent to certain external pins and are connected in series between a test data input pin and a test data output pin in response to the input signal entered to a test control pin, and are operated as a shift register to put in and out signals for testing,

said build-up board further having a common test control pin which is connected in parallel fashion to the test control pins of said semiconductor devices, a common test data input pin, a common test data output pin, and a selection control circuit,

said selection control circuit operating in response to a mode control signal to select a serial connection mode in which said semiconductor devices are connected in series between said common test data input pin and said common test data output pin based on the connection of the test data output pin of one semiconductor device to the test data input pin of another semiconductor device, or select a separate connection mode in which the test data input pin and test data output pin of each semiconductor device are connected to said common test data input pin and common test data output pin individually.

9. An electronic circuit device according to claim 8, wherein said build-up board has a substrate and multi-wiring-layers which are formed on one main surface of said substrate, said multi-wiring-layers having on the surface thereof connection pins which are disposed to mount semiconductor devices and are conductive to certain wiring lines of said multi-wiring-layers, said substrate having on another main surface thereof said external mounting pins which are formed to penetrate said substrate and are conductive to certain wiring lines of said multi-wiring-layers.

10. An electronic circuit device according to claim 9, wherein said semiconductor devices include a microcomputer with CPU and a random access memory, said external mounting pins being adapted to connect to said microcomputer.

11. An electronic circuit device according to claim 10, wherein said microcomputer includes a first electrically-rewritable nonvolatile memory which can store a CPU operation program.

12. An electronic circuit device according to claim 10, wherein said microcomputer includes a memory buffer, which is connected to said random access memory through an exclusive memory bus, said exclusive memory bus being formed on said build-up board without being connected to said external mounting pins

13. An electronic circuit device according to claim 12, wherein said memory buffer has an output buffer which is connected to said exclusive memory bus, said output buffer including in serial connection to the output pin thereof an output MOS transistor and an output impedance controlling MOS transistor which is connected in series to said output MOS transistor, said output impedance controlling MOS transistor having its conduction impedance controlled by receiving on the gate electrode thereof a control voltage which is put out from a voltage generation circuit.

14. An electronic circuit device according to claim 10 further including on one side of said build-up board another semiconductor device which is a programmable device which implements a logic function in a programmable manner in accordance with logic definition data loaded in numerous memory cells, said programmable device being connected to said external mounting pins.

15. An electronic circuit device according to claim 10 further including a mother board which mounts said build-up board as a daughter board, said mother board having a programmable device formed of a semiconductor integrated circuit, which implements a logic function in a programmable manner in accordance with logic definition data loaded in memory cells, said programmable device being connected to said external mounting pins through wiring lines on said mother board.

16. An electronic circuit device comprising a daughter board which mounts a microcomputer and a random access memory, and a mother board which mounts said daughter board and a programmable device which implements a logic function in a programmable manner in accordance with connection definition data loaded in numerous memory cells,

said microcomputer and random access memory being formed on separate semiconductor chips, which are mounted on one side of said daughter board,

said daughter board having on another side thereof external mounting pins for the connection to said mother board,

said external mounting pins being connected to said microcomputer on said daughter board.

17. An electronic circuit device according to claim 16, wherein said microcomputer includes a first electrically-rewritable nonvolatile memory which can store a CPU operation program.

18. An electronic circuit device according to claim 16, wherein said microcomputer includes a memory buffer, which is connected to said random access memory through an exclusive memory bus, said exclusive memory bus being formed on said daughter board without being connected to said external mounting pins.

19. An electronic circuit device according to claim 18, wherein said memory buffer has an output buffer which is connected to said exclusive memory bus, said output buffer including in serial connection to the output pin thereof an output MOS transistor and an output impedance controlling MOS transistor which is connected in series to said output MOS transistor, said output impedance controlling MOS transistor having its conduction impedance controlled by receiving on the gate electrode thereof a control voltage which is put out from a voltage generation circuit.

20. An electronic circuit device comprising as semiconductor devices a microcomputer with CPU and a random access memory,

said microcomputer and random access memory being formed on separate semiconductor chips, which are mounted on one side of a common board different from said semiconductor chips,

said common board having on another side thereof external mounting pins for the connection to other circuit board,

said external mounting pins being adapted to connect to said microcomputer,

said microcomputer having a memory buffer, which is connected to said random access memory through an exclusive memory bus, said exclusive memory bus being formed on said common board without being connected to said external mounting pins.

21. An electronic circuit device according to claim 20, wherein said memory buffer has an output buffer which is connected to said exclusive memory bus, said output buffer including in serial connection to the output pin thereof an output MOS transistor and an output impedance controlling MOS transistor which is connected in series to said output MOS transistor, said output impedance controlling MOS transistor having its conduction impedance controlled by receiving on the gate electrode thereof a control voltage which is put out from a voltage generation circuit.

22. An electronic circuit device according to claim 21, wherein said common board has a glass substrate and multi-wiring-layers which are formed on one main surface of said glass substrate, said multi-wiring-layers having on the surface thereof connection pins which are disposed to mount semiconductor devices and are conductive to certain wiring lines of said multi-wiring-layers, said glass substrate having on another main surface thereof said external mounting pins which are formed to penetrate said glass substrate and are conductive to certain wiring lines of said multi-wiring-layers.

23. An electronic circuit device according to claim 20, wherein said microcomputer includes a first electrically-rewritable nonvolatile memory which can store a CPU operation program.