Ultra dense trench-gated power device with the reduced drain-source feedback capacitance and Miller charge

• US 20040061171A1
• Filed: 10/01/2003
• Published: 04/01/2004
• Est. Priority Date: 03/09/2001
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Jun Zeng
• Inventors: Zeng, Jun
• Granted Patent: US 6,929,988 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/749 with turn-on by field effect
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Claims

1. A semiconductor device having improved and reduced Miller capacitance in a repeated cellular structure, wherein the cells of the device comprise:

a substrate having a first layer highly doped with a first conductivity dopant and formung a drain,

a second layer over the first layer and lightly doped with a first conductivity dopant,

a third layer over the second layer and doped with a second conductivity dopant opposite in polarity to the first conductivity component,

a fourth layer on the opposite surface of the semiconductor substrate and highly doped with a first conductivity dopant;

a trench structure extending from the fourth layer into the substrate and dividing the fourth layer into a plurality of source regions and having a sidewall adjacent the third and fourth layers for controlling a channel in the third layer,

said trench having upper and lower conductive layers separated by a dielectric layer.

2. The semiconductor device of claim 1 wherein the conductive layers in the trench comprise doped polysilicon.

3. The semiconductor device of claim 1 wherein the dielectric layer separating the two conductive layers is silicon nitride.

4. The semiconductor device of claim 1 wherein the upper conductive layer in the trench forms a gate electrode for controlling current through a channel adjacent the sidewall of the trench.

5. The semiconductor device of claim 4 wherein the bottom of the upper conductive layer is approximately on the same level as the bottom of the third layer of second conductivity.

6. The semiconductor device of claim 1 wherein the top of the lower conductive layer is below the bottom of the third layer of second conductivity.

7. The semiconductor device of claim 1 further comprising a source metal layer over the device and in electrical contact with the fourth layer to contact the source regions and in electrical contact with the lower conductive layer of the trenches at peripheral locations around the cells of the device.

8. The semiconductor device of claim 7 wherein the source metal is in contact with the third layer of the second conductivity type.

9. The semiconductor device of claim 1 further comprising a second interlevel dielectric layer above said upper conductive layer.

10. The semiconductor device of claim 9 wherein said second interlevel dielectric layer is borophosphosilicate glass.

11. The semiconductor device of claim 1 wherein the sidewalls and floor of said trench include an oxide layer.

12. The semiconductor device of claim 1 wherein the first dopant is p-type and the second dopant is n-type.

13. The semiconductor device of claim 1 wherein the first dopant is n-type and the second dopant is p-type.

14. A method for forming a semiconductor device with reduced Miller capacitance comprising the steps of:

heavily doping a substrate with a first conductivity dopant to form a drain region;

growing an epitaxial layer on the substrate and lightly doping the epitaxial layer with a dopant of the first conductivity;

implanting the surface of the epitaxial layer with dopants of a second polarity opposite in polarity to the first conductivity dopant;

covering the substrate with a trench mask having openings corresponding to desired trench regions and removing material from the exposed regions to form trenches;

growing an oxide layer on the trench walls and floor and diffusing the second conductivity dopant to form well regions adjacent the trench sidewalls;

in said trench regions forming upper and lower conductive layers and separating the layers with a first dielectric layer;

forming source regions in the surface of the epitaxial layer with dopant of the first conductivity.

15. The method of claim 14 comprising the further step of covering the wafer with a source metal region.

16. The method of claim 14 comprising the further step of connecting the source metal regions to the lower conductive trench layers at locations proximate the periphery of the semiconductor device.

17. The method of claim 14 wherein the dopant of the first conductivity is p-type and the dopant of the second conductivity is n-type.

18. The method of claim 14 wherein the dopant of the first conductivity is n-type and the dopant of the second conductivity is p-type.

19. The method of claim 14 wherein the bottom of the upper conductive layer is approximately on the same level as the bottom of the of the third layer of second conductivity.

20. The method of claim 14 wherein the dielectric layer separating the two conductive layers is silicon nitride.

21. The method of claim 14 further comprising the step of adding a second interlevel dielectric layer above said upper conductive layer.

22. The method of claim 21 wherein said second interlevel dielectric layer isborophosphosilicate glass.