Nonvolatile memory device with configuration switching the number of memory cells used for one-bit data storage

• US 20040062074A1
• Filed: 04/10/2003
• Published: 04/01/2004
• Est. Priority Date: 09/30/2002
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ooishi, Tsukasa
• Granted Patent: US 6,791,869 B2
• Time in Patent Office: Days
• US Class Current: 365/158
• CPC Class Codes: G11C 11/15 using multiple magnetic layers G11C11/155 takes precedence
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1693 Timing circuits or methods
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 7/1015 Read-write modes for single port memories, i.e. having either a random port or a serial port
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators

Abstract

A memory cell array has a plurality of memory cells and dummy memory cells. A column select portion switches access control to a memory cell in accordance with a mode control signal. The column select portion selects one memory cell column to connect a first or second bit line connected with one selected memory cell and first and second reference data lines connected with the dummy memory cells to a data read circuit in a first mode. The column select portion connects the first and second bit lines respectively connected to paired two selected memory cells storing data complimentary to each other to the data read circuit in a second mode.

Claims

1. A nonvolatile memory device comprising:

a memory cell array having a plurality of memory cells arranged in a matrix, each of said plurality of memory cells having a passing current in reading data changed in first and second states respectively in accordance with levels of binary stored data;

an access control circuit for switching access to said plurality of memory cells based on an input address between a first mode in which each of said plurality of memory cells stores one-bit data and a second mode in which each pair of two of said plurality of memory cells stores one-bit data;

a data read circuit performing a data read from a selected portion of said plurality of memory cells that is selected to be accessed by said access control circuit; and

a data write circuit performing a data write into said selected portion of said plurality of memory cells.

2. The nonvolatile memory device according to claim 1, wherein

said access control circuit controls switching of said access in accordance with an electrical signal.

3. The nonvolatile memory device according to claim 1, wherein

said access control circuit selects one memory cell of said plurality of memory cells as said selected portion in accordance with said address signal in said first mode, and

said access control circuit selects two memory cells forming said pair selected to be accessed as said selected portion in accordance with said address signal in said second mode.

4. The nonvolatile memory device according to claim 3, wherein

said data write circuit writes data at complimentary levels respectively into said two memory cells selected by said access control circuit in said second mode.

5. The nonvolatile memory device according to claim 3, wherein

said memory cell array further includes a dummy cell provided to be compared with one of said plurality of memory cells in reading data,

said data read circuit performs said data read based on a comparison of respective access to said one memory cell selected by said access control circuit and to said dummy cell in said first mode, and

said data read circuit performs said data read based on respective access to said two memory cells selected by said access control circuit in said second mode.

6. The nonvolatile memory device according to claim 5, wherein

said data read circuit includes

a first node electrically connected to said one memory cell and one of said two memory cells selected by said access control circuit in said first and second modes, respectively,

a second node,

a first amplifier outputting a voltage produced by amplifying one of a voltage difference and a current difference between said first and second nodes,

a first switch circuit electrically connecting said dummy cell to said first node in said first mode and electrically coupling the other of said two memory cells selected by said access control circuit to said first node in said second mode,

a second amplifier amplifying a voltage difference between said voltage output from said first amplifier and a third node,

a second switch electrically connecting an output node of said second amplifier and said third node during a prescribed period after an operation of said reading data is started, and electrically isolating said output node from said third node after said prescribed period, and

a latch circuit generating read data in accordance with a voltage at said output node after said prescribed period.

7. The nonvolatile memory device according to claim 1, wherein

two memory cells forming same said pair share one of a memory cell row and a memory cell column.

8. The nonvolatile memory device according to claim 1, wherein

said plurality of memory cells are arranged to be divided into a plurality of memory cell blocks,

said access control circuit selects two memory cells respectively belonging to different ones of said plurality of memory cell blocks as said selected portion in said second mode, and

said two memory cells are selected by a common address signal respectively in said different ones of memory cell blocks.

9. The nonvolatile memory device according to claim 1, wherein

a plurality of said memory cell arrays are provided,

said access control circuit, said data read circuit and said data write circuit are provided corresponding to each of said plurality of memory cell arrays, and

a plurality of said access control circuits respectively corresponding to said plurality of memory cell arrays control switching of said access respectively in accordance with independent electrical signals.

10. The nonvolatile memory device according to claim 1, wherein

each of said plurality of memory cells has

a first magnetic layer having a fixed magnetization direction,

a second magnetic layer magnetized in a direction corresponding to a magnetic field created by a data write current controlled in accordance with a level of data to be written, and

an insulating film formed between said first and second magnetic layers.

11. The nonvolatile memory device according to claim 1, wherein

each of said plurality of memory cells has

a heater element generating heat with a data write current controlled in accordance with a level of data to be written and

a phase changing element heated by said heater element for allowing for a transition between two different phase states.

12. A nonvolatile memory device comprising:

a plurality of memory cells each having a passing current in reading data changed in first and second states respectively in accordance with levels of binary stored data;

a plurality of dummy cells provided to be compared with said plurality of memory cells in said reading data and having same characteristic as said plurality of memory cells, wherein

at least ones of said plurality of dummy cells are respectively set to said first and second states; and

a data read circuit, based on access to a selected memory cell selected to be accessed of said plurality of memory cells and to said plurality of dummy cells, reading said stored data from said selected memory.

13. The nonvolatile memory device according to claim 12, wherein

said plurality of memory cells are arranged in rows and columns,

said plurality of dummy cells are arranged to form a plurality of dummy cell columns to share said rows with said plurality of memory cells,

each of dummy cells belonging to one of said plurality of dummy cell columns is set to said first state, and

each of dummy cells belonging to another one of said plurality of dummy cell columns is set to said second state.

14. The nonvolatile memory device according to claim 12, wherein

said data read circuit reads said stored data in said selected memory cell in accordance with a comparison of respective access to one of said plurality of memory cells that is set to said first state and to said selected memory cell and a comparison of respective access to another one of said plurality of memory cells that is set to said second state and to said selected memory cell.

15. The nonvolatile memory device according to claim 12, further comprising:

a first reference data line electrically connected to one of said plurality of dummy cells that is set to said first state in said reading data;

a second reference data line electrically connected to another one of said plurality of dummy cells that is set to said second state in said reading data; and

a switch for making a short circuit between said first and second reference data lines in said reading data, wherein

said data read circuit reads said stored data in said selected memory cell based on one of a current difference and a voltage difference between at least one of said first and second reference data lines and said selected memory cell.

16. A nonvolatile memory device comprising:

a plurality of memory cell blocks; and

a data read circuit provided to be shared by said plurality of memory cell blocks,

each of said plurality of memory cell blocks including

a plurality of memory cells each having a passing current in reading data changed in first and second states respectively in accordance with levels of binary stored data and

a plurality of dummy cells provided to be compared with said plurality of memory cells in said reading data and having same characteristics as said plurality of memory cells, wherein

one of said plurality of memory cells is selected as a read target memory cell from which data is to be read in one of said plurality of memory cell blocks, and

said data read circuit reads said stored data from said read target memory cell based on respective access to said read target memory cell and to one of said plurality of dummy memory cells included in another one of said plurality of memory cell blocks.

17. The nonvolatile memory device according to claim 16, wherein

in each of said plurality of memory cell blocks, said plurality of memory cells are arranged in rows and columns, and said plurality of dummy cells are arranged to form a dummy cell row to share said columns with said plurality of memory cells,

each of said plurality of memory cell blocks further includes a plurality of bit lines provided corresponding to said columns, and

said data read circuit is electrically connected to one of said plurality of bit lines included in said one of said plurality of memory cells that corresponds to said read target memory cell and one of said plurality of bit lines included in said another one of said plurality of memory cell blocks.

18. The nonvolatile memory device according to claim 16, wherein

each of said plurality of memory cells has a first electric resistance and a second electric resistance higher than said first resistance in said first and second states, respectively,

said data read circuit includes

a resistance applying circuit for applying an electric resistance smaller than a difference between said first and second electric resistances to a first current path including said one of said plurality of dummy cells and

an amplifier amplifying a passing current difference between a second current path including said read target memory cell and said first current path, and

said data read circuit reads said stored data from said read target memory cell in accordance with an output of said amplifier.