ELECTRONIC FINGERPRINTING OF SEMICONDUCTOR INTEGRATED CIRCUITS

• US 20040062084A1
• Filed: 09/30/2002
• Published: 04/01/2004
• Est. Priority Date: 09/30/2002
• Status: Active Grant

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Agere Systems Incorporated (Broadcom, Inc.)
• Inventors: Chaudhry, Samir, Thomson, J. Ross, Layman, Paul Arthur, Norman, James Gary
• Granted Patent: US 6,738,294 B2
• Time in Patent Office: Days
• US Class Current: 365/189.01
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: H01L 2223/5444 for electrical read out

Abstract

A method of identifying an integrated circuit device based on the initial state of certain memory cells within a memory array of the integrated circuit device. For many cells in the memory array the initial state is relatively consistent at each power-up, due to mismatches between the transistors that form each memory cell. Thus these consistent initial states provide a signature of the memory array and the integrated circuit device.

Claims

1. A method for identifying an integrated circuit device including memory cells therewith, comprising:

(a) applying power to the memory cells;

(b) determining the initial state of the memory cells;

(c) repeating the steps (a) and (b) until a plurality of the memory cells are determined to exhibit an initial state that is relatively consistent each time the step (a) is executed; and

(d) associating the initial state of the plurality of memory cells with the integrated circuit device.

2. The method of claim 1 wherein the plurality of memory cells comprise a static random access memory.

3. The method of claim 1 wherein the initial state is represented by a binary “

0”

or a binary “

1”

.

4. The method of claim 1 wherein the integrated circuit device is one of a plurality of integrated circuit devices formed from a semiconductor wafer, and wherein the initial state of the plurality of memory cells is associated with the semiconductor wafer from which the integrated circuit device was formed.

5. The method of claim 1 wherein the integrated circuit device is one of a plurality of integrated circuit devices formed from a semiconductor wafer during fabrication of a wafer lot, and wherein the initial state of the plurality of memory cells is associated with the wafer lot from which the integrated circuit device was formed.

6. The method of claim 1 wherein the integrated circuit device is formed during processing steps, and wherein the initial state of the plurality of memory cells is associated with the processing steps.

7. The method of claim 1 wherein the step (d) further comprises forming a map of the plurality of memory cells, wherein the map identifies the position of the plurality of memory cells and the initial state of each one of the plurality of memory cells.

8. The method of claim 7 wherein the step (d) further comprises associating the map with the integrated circuit device.

9. The method of claim 1 wherein each one of the plurality of memory cells comprises cross-coupled inverters.

10. The method of claim 9 wherein the cross-coupled inverters comprise active devices, and wherein the active devices are selected from among complimentary MOSFETs, NMOSFETs, PMOSFETs and bipolar transistor devices.

11. A method for manufacturing semiconductor devices, comprising:

(a) providing a semiconductor substrate;

(b) performing semiconductor fabrication processes on the semiconductor substrate to form semiconductor devices thereon, wherein the semiconductor substrate comprises a plurality of semiconductor die, and wherein each die comprises a plurality of semiconductor devices, and wherein certain of the die include memory cells;

(c) applying power to the memory cells of each die comprising memory cells;

(d) determining the initial state of the memory cells;

(e) repeating the steps (c) and (d) until a plurality of the memory cells on a die are determined to exhibit an initial state that is relatively consistent each time the step (c) is executed;

(f) associating the initial state of the plurality of memory cells with the die on which the memory cells are located;

(g) singulating the semiconductor substrate into individual die; and

(h) maintaining the association after the die are singulated.

12. The method of claim 11 wherein the step (f) further comprises associating the initial state of the plurality of memory cells with indicia related to the semiconductor substrate.

13. The method of claim 11 wherein the step (f) further comprises associating the initial state of the plurality of memory cells with the semiconductor fabrication processes performed on the semiconductor substrate according to the step (b).