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TCP/IP offload device

  • US 20040062245A1
  • Filed: 04/22/2003
  • Published: 04/01/2004
  • Est. Priority Date: 04/22/2002
  • Status: Active Grant
First Claim
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1. A system, comprising:

  • (a) fast-path receive circuitry that is in control of a first plurality of TCP/IP connections, a first TCP/IP packet associated with one of the first plurality of TCP/IP connections being received onto the fast-path circuitry from a network, the fast-path receive circuitry comprising;

    an SRAM that stores a control block (CB) for each TCP/IP connection of a first set of the first plurality of TCP/IP connections;

    a DRAM that stores a CB for each TCP/IP connection of a second set of the first plurality of TCP/IP connections, the DRAM storing a CB associated with the first TCP/IP packet received onto the fast-path receive circuitry;

    a content addressable memory (CAM); and

    a first processor that executes a receive state machine, the first processor obtaining from the CAM information indicative of whether the CB associated with the first TCP/IP packet is stored in the SRAM or is stored in the DRAM, the first processor using the information obtained from the CAM to access the CB; and

    (b) a processor that executes a protocol processing stack, the protocol processing stack being in control of a second plurality of TCP/IP connections, wherein TCP/IP packets associated with the second plurality of TCP/IP connections are received onto the fast-path circuitry from the network, the protocol processing stack performing TCP protocol processing on the TCP/IP packets associated with the second plurality of TCP/IP connections, and wherein other TCP/IP packets associated with the first plurality of TCP/IP connections are received onto the fast-path circuitry from the network, the protocol stack performing substantially no TCP protocol processing on the other TCP/IP packets associated with the second plurality of TCP/IP connections.

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