TCP/IP offload device

• US 20040062245A1
• Filed: 04/22/2003
• Published: 04/01/2004
• Est. Priority Date: 04/22/2002
• Status: Active Grant

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Philbrick, Clive M., Starr, Daryl D., Blightman, Stephen E.J., Sharp, Colin C.
• Granted Patent: US 7,496,689 B2
• Time in Patent Office: Days
• US Class Current: 370/392
• CPC Class Codes: H04L 69/10 Streamlined, light-weight or high-speed protocols, e.g. express transfer protocol [XTP] or byte stream
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/163 In-band adaptation of TCP data exchange; In-band control procedures

Abstract

A TCP/IP offload network interface device (NID) is integrated with a processing device that executes a stack. The TCP/IP offload NID can either be a full TCP/IP offload device or a partial TCP/IP offload device. Common types of packets are processed by the NID in a fast-path such that the stack is offloaded of TCP and IP protocol processing tasks. A hash is made from the packet header and is pushed onto a queue. The hash is later popped off the queue and is used to identify an associated TCB number from a hash table. A mechanism caches hash buckets in SRAM and stores other hash buckets in DRAM. An “IN SRAM CAM” is used to determine whether the TCB associated with the identified TCB number is cached in SRAM or whether it must be moved from DRAM into the SRAM cache. A lock table and a “lock table CAM” mechansim is disclosed that facilitates multiple processors working on the protocol processing of a single packet.

Claims

1. A system, comprising:

(a) fast-path receive circuitry that is in control of a first plurality of TCP/IP connections, a first TCP/IP packet associated with one of the first plurality of TCP/IP connections being received onto the fast-path circuitry from a network, the fast-path receive circuitry comprising;

an SRAM that stores a control block (CB) for each TCP/IP connection of a first set of the first plurality of TCP/IP connections;

a DRAM that stores a CB for each TCP/IP connection of a second set of the first plurality of TCP/IP connections, the DRAM storing a CB associated with the first TCP/IP packet received onto the fast-path receive circuitry;

a content addressable memory (CAM); and

a first processor that executes a receive state machine, the first processor obtaining from the CAM information indicative of whether the CB associated with the first TCP/IP packet is stored in the SRAM or is stored in the DRAM, the first processor using the information obtained from the CAM to access the CB; and

(b) a processor that executes a protocol processing stack, the protocol processing stack being in control of a second plurality of TCP/IP connections, wherein TCP/IP packets associated with the second plurality of TCP/IP connections are received onto the fast-path circuitry from the network, the protocol processing stack performing TCP protocol processing on the TCP/IP packets associated with the second plurality of TCP/IP connections, and wherein other TCP/IP packets associated with the first plurality of TCP/IP connections are received onto the fast-path circuitry from the network, the protocol stack performing substantially no TCP protocol processing on the other TCP/IP packets associated with the second plurality of TCP/IP connections.

2. The system of claim 1, wherein the first processor accesses the CB associated with the first TCP/IP packet by causing the CB to be copied from the DRAM into the SRAM.

3. The system of claim 1, wherein the fast-path receive circuitry generates a hash for the first TCP/IP packet, and wherein the fast-path receive circuitry pushes the hash onto a queue, the first processor popping the queue and thereby obtaining the hash, the first processor then using the hash to identify the control block (CB) associated with the first TCP/IP packet.

4. The system of claim 1, wherein the SRAM includes a plurality of control block (CB) slots, and wherein the CAM contains a CAM entry for each of the CB slots in the SRAM.

5. The system of claim 1, wherein the control block (CB) associated with the first TCP/IP packet contains TCP state information.

6. The system of claim 1, wherein the control block (CB) associated with the first TCP/IP packet is a communication control block (CCB).

7. The system of claim 1, wherein the control block (CB) associated with the first TCP/IP packet is a transmit control block (TCB), the TCB comprising:

TCP state information, a TCP source port address, a TCP destination port address, an IP source address, and an IP destination address.

8. The system of claim 1, wherein the fast-path receive circuitry further comprises:

a second processor that executes the receive state machine, the first processor and the second processor together performing TCP protocol processing and IP protocol processing on the first TCP/IP packet.

9. The system of claim 8, wherein one of the first and second processors performs initial processing on the first TCP/IP packet using the receive state machine and then stops processing the first TCP/IP packet and stores state information relating to a state of the receive state machine, and wherein the other the first and second processors retrieves the state information and uses the retrieved state information to perform subsequent processing on the first TCP/IP packet using the receive state machine.

10. The system of claim 1, wherein the fast-path receive circuitry uses a plurality of hash buckets to identify control blocks (CBs) associated with incoming TCP/IP packets, some of the plurality of hash buckets being cached in the SRAM, others of the hash buckets being stored in DRAM.

11. The system of claim 10, wherein the first TCP/IP packet has an associated hash bucket, wherein if the associated hash bucket is stored in DRAM, then the associated hash bucket is copied into the SRAM, the associated hash bucket having a hash bucket entry, the first processor checking the hash bucket entry to determine whether TCP and IP fields of the hash bucket entry match TCP and IP fields of the first TCP/IP packet.

12. The system of claim 1, wherein the fast-path receive circuitry further comprises:

a plurality of lock bits, there being one lock bit for each of the first plurality of TCP/IP connections controlled by the fast-path receive circuitry, a lock bit indicating whether a control block (CB) associated with the lock bit has been locked by a processor context;

a lock table CAM; and

a lock table, wherein the lock table and the lock table CAM are used to identify a processor context that is waiting to gain control of the control block (CB).

13. The system of claim 12, wherein the lock table contains a plurality of entries, each entry identifying one of a plurality of processor contexts.

14. The system of claim 1, wherein each CB of the second set of the first plurality of TCP/IP connections is also stored in the SRAM.

15. The system of claim 1, further comprising a host CPU, the fast-path receive circuitry (a) and the processor (b) being part of a network interface device, the network interface being coupled to the host CPU.

16. The system of claim 1, wherein the fast-path receive circuitry (a) is part of a network interface device, and wherein the processor (b) is a host CPU, the network interface device being coupled to the host CPU.

17. A system, comprising:

a first processor that executes a protocol processing stack; and

fast-path receive circuitry that receives an incoming TCP/IP packet and performs substantially all TCP and IP protocol processing on the TCP/IP packet, the TCP/IP packet containing a header portion and a data portion, the data portion being transferred into a destination identified by the first processor, the data portion being transferred without the header portion being transferred into the destination and without the protocol processing stack doing any TCP protocol processing on the TCP/IP packet, the fast-path receive circuitry comprising;

an SRAM that stores a first plurality of control blocks (CB);

a DRAM that stores a second plurality of control blocks (CB);

a content addressable memory (CAM); and

a second processor that executes a receive state machine, the second processor using the CAM to determine whether a control block (CB) associated with the incoming TCP/IP packet is stored in the SRAM, wherein if the control block is not stored in the SRAM but rather is stored in the DRAM, then the second processor causes the control block (CB) associated with the incoming TCP/IP packet to be copied into the SRAM.

18. The system of claim 17, wherein the incoming TCP/IP packet is associated with a TCP/IP connection, wherein control of the TCP/IP connection is passed from the first processor to the fast-path receive circuitry.

19. The system of claim 18, wherein control of the TCP/IP connection is passed to the fast-path receive circuitry by passing control of an associated control block (CB) to the fast-path receive circuitry.

20. A method, comprising:

receiving a TCP/IP packet onto a network interface device;

generating a hash from the TCP/IP packet and pushing the hash onto a queue, the queue being located on the network interface device;

popping the queue to retrieve the hash and using the hash to identify a hash bucket;

determining that the hash bucket identified by the hash is stored in a DRAM and copying the hash bucket from the DRAM and into an SRAM, the DRAM and the SRAM both being part of the network interface device;

searching a plurality of hash entries in the identified hash bucket and determining from one of the hash entries a control block number;

using a content addressable memory (CAM) to determine that a control block (CB) associated with the control block number is located in the DRAM, the CAM being part of the network interface device;

copying the control block (CB) from the DRAM and into the SRAM; and

using the control block (CB) to fast-path process the TCP/IP packet on the network interface device, the network interface device transferring a data portion of the TCP/IP packet into a destination, the destination having been identified by a processor, the processor executing a protocol processing stack, the network interface device transferring the data portion into the destination identified by the processor without the protocol processing stack of the processor performing any TCP protocol processing on the TCP/IP packet.

21. The method of claim 20, wherein the processor is a CPU of a host computer, the network interface device being coupled to the host computer, the destination being located in a memory of the host computer.

22. The method of claim 20, wherein the processor is a part of the network interface device.