×

Calculation of clock skew using measured jitter buffer depth

  • US 20040062252A1
  • Filed: 09/30/2002
  • Published: 04/01/2004
  • Est. Priority Date: 09/30/2002
  • Status: Active Grant
First Claim
Patent Images

1. A system for calculation of clock skew between two communication ports in a packet network, comprising:

  • a transmitting unit comprising a transmitting clock a receiving unit comprising a playout clock, a FIFO playout buffer, and a resampling unit;

    a packet data stream between the transmitting unit and the receiving unit;

    a packet sample buffer in the resampling unit that receives packet data from the playout buffer and feeds a resampler;

    a timing logic module that generates a timing phase signal based on the size change of the playout buffer combined with the packet sample buffer, where the signal tracks the clock frequency offset between the transmitting and playout clocks;

    a resampler in the sampling unit that resamples the packet data from the sample packet buffer and uses the timing phase signal to advance or retard the sampling phase of a bank of subfilters within said resampler.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×