Determining an optimal sampling clock

• US 20040062329A1
• Filed: 09/30/2002
• Published: 04/01/2004
• Est. Priority Date: 09/30/2002
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Volk, Andrew M., Hsu, Jen-Tai, To, Hing-Yan
• Granted Patent: US 7,245,682 B2
• Time in Patent Office: Days
• US Class Current: 375/355
• CPC Class Codes: H04L 7/0332 with an integrator-detector
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop

Abstract

In some embodiments, a phase detector receives a set of sampling clock signals and a data signal and compares each of the clock signals to the data signal. A clock selector selects an optimal sampling clock signal from the set of sampling clock signals based on a trend of a relationship between the clock signals and the data signal. Other embodiments are described and claimed.

Claims

1. A method comprising:

determining a trend in a relationship between clock signals and received data based on information included in the received data; and

identifying a first clock as an optimal sampling clock for the data based on the trend.

2. The method of claim 1 in which the first clock is chosen from among a set of sampling clocks of different phases.

3. The method of claim 1 in which the first clock is identified using a quadrature phase detector.

4. The method of claim 1, also including sending an alignment sequence.

5. The method of claim 1, in which the information included in the received data includes pre-determined data.

6. The method of claim 1, also including storing information about characteristics of a previously optimal sampling clock.

7. The method of claim 1, also including:

identifying a change in the relationship between the clock signals and the data, in which the first clock is no longer an optimal sampling clock for the data; and

identifying a second clock as an optimal sampling clock for the data.

8. The method of claim 7, also including determining the refresh rate time between the identification of the first clock as an optimal sampling clock and the identification of the second clock as an optimal sampling clock.

9. The method of claim 8, also including changing the sampling clock after a time period equal to the refresh rate time.

10. The method of claim 9, also including:

programming an RC time constant value of a low pass filter based on the refresh rate time; and

using the low pass filter to change the optimal sampling clock based on the RC time constant value.

11. Apparatus comprising:

a phase detector to receive a set of sampling clock signals and a data signal and to compare each of the clock signals to the data signal; and

a clock selector to select an optimal sampling clock signal from the set of sampling clock signals based on a trend of a relationship between the clock signals and the data signal.

12. The apparatus of claim 11, also including:

comparison signals, corresponding to each of the sampling clock signals, generated by the phase detector, each comparison signal representing information indicative of a time period during which the data signal and the sampling clock signal match or do not match.

13. The apparatus of claim 12, in which each comparison signal represents:

a first time period, during which both the data signal and the sampling clock signal are at one logic level, and

a subsequent time period, during which the data signal and the sampling clock are at different logic levels.

14. The apparatus of claim 13, in which the phase detector includes an analog circuit having a capacitor corresponding to each comparison signal, each capacitor arranged to charge during the first time period and discharge during the subsequent time period.

15. The apparatus of claim 13, in which the phase detector includes a quadrature phase detector.

16. The apparatus of claim 11, in which the clock selector includes a winner-take-all circuit.

17. The apparatus of claim 11, in which the clock selector includes a low pass filter.

18. The apparatus of claim 17, in which the low pass filter is programmable.

19. A system comprising:

a receiver to receive the data signal from a transmitter;

a clock generator to generate a set of sampling clocks;

a clock determination module connected to the receiver and clock generator to compare the data signal to the set of clocks to determine an optimal sampling clock based on a trend in the relationship of the data signal to the clocks; and

a sampling system to sample the data with the optimal sampling clock.

20. The system of claim 19, in which the clock determination module includes a quadrature phase detector.

21. The system of claim 19, in which the clock determination module includes comparison signals, corresponding to each clock, each comparison signal representing information indicative of a time period during which the data signal and the clock match or do not match.

22. The system of claim 21, in which:

each comparison signal represents information indicative of a first time period, during which both the data signal and the sampling clock signal are at one logic level, and a subsequent time period, during which the data signal and the sampling clock are at different logic levels; and

the clock determination module includes an analog circuit having a capacitor corresponding to each comparison signal that charges during the first time period and discharges during the subsequent time period.

23. The system of claim 22, in which the clock determination module includes a winner-take-all circuit to compare the comparison signals.

24. The system of claim 19, in which the clock determination module includes a programmable low pass filter.

25. An article comprising a storage medium having stored thereon instructions that when executed by a machine result in the following:

determining a trend in a relationship between clock signals and received data based on information included in the received data; and

identifying a first clock as an optimal sampling clock for the data based on the trend.

26. The article of claim 25, also including instructions that when executed by a machine result in the following:

identifying the first clock using a quadrature phase detector.

27. The article of claim 25, in which the information included in the received data includes alignment information.

28. The article of claim 25, also including instructions that when executed by a machine result in the following:

identifying a change in the relationship between the clock signals and the data, in which the first clock is no longer an optimal sampling clock for the data; and

identifying a second clock as an optimal sampling clock for the data.

29. the article of claim 28, also including instructions that when executed by a machine result in the following:

determining a refresh rate time between the identification of the first clock as an optimal sampling clock and the identification of the second clock as an optimal sampling clock.

30. The article of claim 29, also including instructions that when executed by a machine results in the following:

changing the sampling clock after a time period equal to the refresh rate time.