Parallel scrambler/descrambler
First Claim
1. A system for processing a set of data bits using a subset of a recurring sequence of scrambler bits, the system comprising:
- receiving means for receiving said set of data bits;
storage means for storing said set of data bits;
digital logic means for determining an appropriate subset of said sequence of scramble bits;
generating means for generating said appropriate subset; and
digital operation means for performing a bitwise parallel digital operation between said appropriate subset and said set of data bits to produce an output set of data bits.
3 Assignments
0 Petitions
Accused Products
Abstract
Systems, methods and devices for scrambling/descrambling sets of data bits using subsets of a recurring sequence of scrambler bits. A self-synchronous scrambler, regardless of the generating polynomial being implemented, will generate repeating sequences of scrambler bits regardless of the initial stage of the scrambler. To implement a parallel scrambler, given a current state of the scrambler, the next n states of the scrambler are predicted based on the current state of the scrambler. The scrambling operation can then be preformed using the values in the current state—parallel logic operations between preselected bits of the current state will yield the required values to be used in scrambling an incoming parallel data set. Once these required values are generated, a parallel logical operation between the required values and the incoming data set will result in the scrambled output data. The current state of the scrambler is then incremented by n+1 by performing a predetermined set of logical operations between the various bits of the current state such that each bit of the n+1 state is a result of a logical operation between selected and predetermined bits of the current state.
96 Citations
16 Claims
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1. A system for processing a set of data bits using a subset of a recurring sequence of scrambler bits, the system comprising:
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receiving means for receiving said set of data bits;
storage means for storing said set of data bits;
digital logic means for determining an appropriate subset of said sequence of scramble bits;
generating means for generating said appropriate subset; and
digital operation means for performing a bitwise parallel digital operation between said appropriate subset and said set of data bits to produce an output set of data bits. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A digital scrambler/descrambler using a subset of a securing sequence of scrambler bits, the scrambler/descrambler comprising:
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selection means for selecting between a first set of data bits to be scrambled and a second set of data bits to be descrambled;
digital logic means for determining an appropriate subset of said sequence of scrambler bits, said appropriate subset being determined based on an immediately preceding subset of said sequence of scrambler bits;
digital operation means for executing a bitwise parallel digital operation between said appropriate subset and either said first or said second set. - View Dependent Claims (9, 10, 11, 12)
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13. A method of processing a plurality of data bits using a subset of a recurring sequence of scrambler bits, the method comprising:
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a) receiving and storing in parallel said plurality of data bits;
b) determining an appropriate subset of said sequence of scrambler bits based on an immediately preceding subset;
c) generating said appropriate subset;
d) loading said appropriate subset in a storage means; and
e) performing a bitwise parallel XOR operation between said appropriate subset and said plurality of data bits. - View Dependent Claims (14, 15, 16)
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Specification