MEASUREMENT OF LATERAL DIFFUSION OF DIFFUSED LAYERS

• US 20040063225A1
• Filed: 09/23/2002
• Published: 04/01/2004
• Est. Priority Date: 09/23/2002
• Status: Active Grant

• Current Assignee: Semiconductor Physics Laboratory, Inc.
• Original Assignee: Applied Materials Incorporated
• Inventors: Paton, Eric, Borden, Peter G., Kluth, G. Jonathan
• Granted Patent: US 6,878,559 B2
• Time in Patent Office: Days
• US Class Current: 438/7
• CPC Class Codes: G01N 2021/8416 and process controlling, not otherwise provided for
• CPC Class Codes: G01N 21/21 Polarisation-affecting properties G01N21/19 takes precedence
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G01N 2201/0691 Modulated (not pulsed supply)
• CPC Class Codes: G01R 31/311 of integrated circuits G01R31/31728 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Any semiconductor wafer fabrication process may be changed to monitor lateral abruptness of doped layers as an additional step in the wafer fabrication process. In one embodiment, a test structure including one or more doped regions is formed in a production wafer (e.g. simultaneously with one or more transistors) and one or more dimension(s) of the test structure are measured, and used as an estimate of lateral abruptness in other doped regions in the wafer, e.g. in the simultaneously formed transistors. Doped regions in test structures can be located at regularly spaced intervals relative to one another, or alternatively may be located with varying spacings between adjacent doped regions. Alternatively or in addition, multiple test structures may be formed in a single wafer, with doped regions at regular spatial intervals in each test structure, while different test structures have different spatial intervals.

Claims

1. A method for evaluating a semiconductor wafer, the method comprising:

forming a test structure of a predetermined geometry in the semiconductor material, said test structure comprising a plurality of areas separated from one another, at least one area in the plurality of areas having different properties as compared to another area in the plurality of areas;

measuring light reflected from said test structure, said reflected light having a component comprising a superposition of reflections of different amplitudes or phases from said areas with differing electronic properties;

analyzing a signal obtained from measuring to determine the extent of lateral diffusion in said region; and

using the extent of lateral diffusion to accept or reject the semiconductor wafer for further processing.

2. The method of claim 1 further comprising:

illuminating at least a portion of the test structure with a first beam to generate a plurality of charge carriers;

illuminating with a second beam to perform said measuring in at least a region of the semiconductor wafer having at least some of the charge carriers in the plurality generated by the first beam.

3. The method of claim 2 wherein:

each of the first beam and the second beam are coincident.

4. The method of claim 2 wherein:

at least one of the first beam and the second beam is polarized.

5. The method of claim 4 wherein:

the test structure includes a plurality of doped regions, each doped region being separated from an adjacent doped region; and

polarization is parallel to each of said doped regions.

6. The method of claim 4 wherein:

each of the first beam and the second beam is polarized.

7. The method of claim 2 further comprising:

modulating intensity of the first beam at a predetermined frequency; and

using the predetermined frequency during said measuring.

8. The method of claim 1 wherein:

the test structure includes a plurality of doped regions.

9. The method of claim 8 wherein:

each doped region is separated from an adjacent doped region by a fixed distance.

10. The method of claim 8 wherein:

each doped region is separated from an adjacent doped region by a different distance.

11. The method of claim 1 wherein:

the test structure is a first test structure comprising a plurality of first doped regions separated each from another by a first distance;

the method further comprises forming in the semiconductor wafer a second test structure comprising a plurality of second doped regions separated each from another by a second distance different from the first distance; and

the method further comprises repeating the acts of illuminating and measuring with the second test structure.

12. A method for evaluating a semiconductor wafer, the method comprising:

forming a test structure of a predetermined geometry in the semiconductor wafers;

measuring a signal indicative of a dimension of the test structure; and

changing a process parameter used in fabrication of the wafer, depending on said signal obtained from said measuring.

13. The method of claim 12 further comprising:

illuminating the test structure with at least one beam of electromagnetic radiation.

14. The method of claim 13 wherein:

said beam is polarized.

15. The method of claim 12 further comprising:

illuminating the test structure with a first beam to generate a plurality of charge carriers; and

illuminating the test structure with a second beam to sense a concentration of the charge carriers generated by the first beam.

16. The method of claim 15 wherein;

the first beam is modulated at a predetermined frequency; and

said predetermined frequency is used during said act of measuring.

17. An apparatus for evaluating a semiconductor wafer, the apparatus comprising:

means for forming a test structure of a predetermined geometry in the semiconductor wafer; and

means for measuring a signal indicative of dimension of the test structure.

18. The apparatus of claim 17 further comprising:

means for illuminating the test structure with a beam of electromagnetic radiation.

19. The apparatus of claim 18 further comprising:

means for modulating coupled to said means for illuminating; and

a lock-in amplifier coupled to said means for measuring.