Organic field-effect transistor, method for structuring and ofet and integrated circuit

• US 20040063267A1
• Filed: 11/17/2003
• Published: 04/01/2004
• Est. Priority Date: 12/08/2000
• Status: Active Grant

• Current Assignee: AMO GmbH, PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Original Assignee: PolyIC GmbH & Co. KG (Leonhard KURZ Stiftung & Company KG)
• Inventors: Vratzov, Borislav, Haring, Peter, Kurz, Heinrich, Bernds, Adolf, Clemens, Wolfgang
• Granted Patent: US 7,229,868 B2
• Time in Patent Office: Days
• US Class Current: 438/202
• CPC Class Codes: H10K 10/464 Lateral top-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/468 characterised by the gate dielectrics
• CPC Class Codes: H10K 71/13 using printing techniques, e.g. ink-jet printing or screen printing
• CPC Class Codes: H10K 71/20 Changing the shape of the active layer in the devices, e.g. patterning
• CPC Class Codes: H10K 71/221 by lift-off techniques
• CPC Class Codes: H10K 71/621 Providing a shape to conductive layers, e.g. patterning or selective deposition
• CPC Class Codes: H10K 71/821 Patterning of a layer by embossing, e.g. stamping to form trenches in an insulating layer

Abstract

The invention relates to an organic fieId-effect transistor, to a method for structuring an OFET and to an integrated circuit with improved structuring of the functional polymer layers. The improved structuring is obtained by introducing, using a doctor blade, the functional polymer in the mold layer in which recesses are initially produced by imprinting.

Claims

1. Organic field-effect transistor (OFET) comprising at least the following layers on a substrate:

an organic semiconductor layer between and above at least one source and at least one drain electrode which are composed of a conducting organic material,

an organic insulation layer over the semiconducting layer and

an organic conductor layer,

wherein the conductor layer and at least one of the two other layers is patterned.

2. OFET according to claim 1, having a distance 1 between source and drain electrode of less than 20 μ

m, particularly of less than 10 μ

m and most preferably of 2 to 5 μ

m.

3. OFET according to one of the claims 1 or 2, comprising an electrode having a layer thickness of 1 μ

m.

4. Integrated circuit, comprising at least one OFET having at least one patterned conductor layer and one further patterned layer.

5. Method for patterning an OFET by introduction, by means of a doctor blade, of at least one functional polymer into a negative mold.

6. Method according to claim 5, comprising the following operating steps:

a) a mold layer for a negative mold is deposited on a substrate or a lower layer,

b) this mold layer is provided with recesses which correspond to the negatives of the subsequent patterns and

c) the functional polymer is then introduced into these recesses by means of a doctor blade.

7. Method according to one of the claims 5 or 6, wherein the mold layer is removed upon completion of the patterning.

8. Method according to one of the claims 5 to 7, wherein the functional polymer is introduced at least twice into the recesses of the mold layer by means of a doctor blade.

9. Method according to one of the claims 5 to 8, wherein the recesses in the mold layer are created by imprinting.

10. Method according to one of the claims 5 to 9, which is performed as a continuous process by means of a continuously running belt.