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Reduction in source-drain resistance of semiconductor device

  • US 20040063289A1
  • Filed: 09/24/2003
  • Published: 04/01/2004
  • Est. Priority Date: 09/30/2002
  • Status: Abandoned Application
First Claim
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1. A semiconductor device manufacture method comprising steps of:

  • (a) forming a gate electrode over each of a plurality of active regions defined in a silicon substrate, said gate electrode traversing a corresponding one of the active regions, and forming extension regions of source/drain in the active region on both sides of said gate electrode;

    (b) depositing first and second insulating films having different etching characteristics on the silicon substrate, said first and second insulating films covering side walls of said gate electrode, and anisotropically etching said first and second insulating films to form a side wall spacer on the side walls of each gate electrode;

    (c) selectively etching said first insulating film of the side wall spacer to form a retraction portion retracted from a surface of said second insulating film on a gate electrode side and on a silicon substrate side;

    (d) implanting ions into the silicon substrate by using the side wall spacer as a mask to form source/drain regions in the silicon substrate; and

    (e) depositing metal capable of silicidation over the silicon substrate and performing a silicidation reaction and form silicide regions.

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