Wafer-level transfer of membranes with gas-phase etching and wet etching methods

• US 20040063322A1
• Filed: 10/02/2003
• Published: 04/01/2004
• Est. Priority Date: 11/02/2000
• Status: Active Grant

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Yang, Eui-Hyeok
• Granted Patent: US 7,268,081 B2
• Time in Patent Office: Days
• US Class Current: 438/689
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81B 2203/0361 Tips, pillars
• CPC Class Codes: B81C 1/00357 involving bonding one or several substrates on a non-temporary support, e.g. another substrate
• CPC Class Codes: B81C 2201/019 Bonding or gluing multiple substrate layers
• CPC Class Codes: B81C 2201/0191 Transfer of a layer from a carrier wafer to a device wafer
• CPC Class Codes: B81C 2203/038 Bonding techniques not provided for in B81C2203/031 - B81C2203/037
• CPC Class Codes: B81C 3/001 Bonding of two components
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: Y10S 438/928 Front and rear surface processing
• CPC Class Codes: Y10S 438/968 Semiconductor-metal-semiconductor

Abstract

Techniques for transferring a membrane from one wafer to another wafer to form integrated semiconductor devices. In one implementation, a carrier wafer is fabricated to include a membrane on one side of the carrier wafer. The membrane on the carrier wafer is then bond to a surface of a different, device wafer by a plurality of joints. Next, the carrier wafer is etched away by a dry etching chemical to expose the membrane and to leave said membrane on the device wafer. Transfer of membranes with a wet etching process is also described.

Claims

11. A method, comprising:

preparing a carrier wafer to have a support wafer made of a semiconductor material, a carrier passivation layer formed on a surface of the support wafer, a membrane formed on the carrier passivation layer, and a plurality of metal posts on the membrane, wherein the carrier passivation layer is inert to a gaseous etchant that etches the semiconductor material;

patterning a surface of a device wafer made from the semiconductor material to form a plurality of metal posts respectively corresponding to the metal posts on the membrane;

placing the carrier wafer on the device wafer to have metal posts on the membrane directly contact metal posts on the device wafer, respectively;

forming direct metal-to-metal bonding between contacting metal posts to bond the carrier wafer to the device wafer;

forming a passivation layer on exterior surfaces of the device wafer while leaving the support wafer exposed;

exposing the bonded carrier wafer and the device wafer to the gaseous etchant to etch away the support wafer in the carrier wafer and to expose the carrier passivation layer; and

removing the carrier passivation layer to transfer the membrane to the device wafer.

12. The method as in claim 11, wherein the semiconductor material is silicon and the gaseous etchant is XeF₂.

13. The method as in claim 12, wherein the carrier passivation layer in the carrier wafer and the passivation layer on the device wafer are silicon oxide.

14. The method as in claim 12, wherein the carrier passivation layer is about 100 angstroms.

15. The method as in claim 12, wherein the membrane is less than one micron in thickness.

16. The method as in claim 11, further comprising:

forming a through hole through the device wafer to connect the surface of the device wafer and an opposing surface of the device wafer; and

bonding a back wafer to the opposing surface of the device wafer to cover the through hole.

17. The method as in claim 16, further comprising patterning the back wafer to have a sealing pattern around the through hole to seal the through hole.

18. The method as in claim 17, further comprising:

after the removal of the carrier passivation layer, patterning the back wafer to expose the through hole through the back wafer.

19. The method as in claim 11, wherein the metal posts on the membrane and the device wafer are made of indium.

20. A method, comprising:

preparing a carrier wafer to have a support wafer made of silicon, a carrier passivation layer formed on a surface of the support wafer, a membrane formed on the carrier passivation layer, and a plurality of posts on the membrane, wherein the carrier passivation layer is inert to a gaseous etchant that etches silicon;

placing the carrier wafer on a device wafer to bond the posts to the device wafer;

forming a passivation layer on exterior surfaces of the device wafer while leaving the support wafer exposed;

exposing the bonded carrier wafer and the device wafer to the gaseous etchant to etch away the support wafer in the carrier wafer and to expose the carrier passivation layer; and

removing the carrier passivation layer to transfer the membrane to the device wafer.

1. A method, comprising:

preparing a carrier wafer to have a support wafer made of a semiconductor material, a carrier passivation layer formed on a surface of the support wafer, and a membrane formed on the carrier passivation layer, wherein the carrier passivation layer is inert to a gaseous etchant that etches the semiconductor material;

patterning a surface of a device wafer made from the semiconductor material to form a plurality of posts, each post having a top flat surface;

forming a passivation layer on exterior surfaces of the device wafer without covering each top flat surface of each post;

placing the carrier wafer on the device wafer to have the membrane directly contact top flat surfaces of the posts;

forming a direct semiconductor-to-semiconductor bonding between the membrane and the top flat surfaces to bond the carrier wafer to the device wafer;

exposing the bonded carrier wafer and the device wafer to the gaseous etchant to etch away the support wafer in the carrier wafer and to expose the carrier passivation layer; and

removing the carrier passivation layer to transfer the membrane to the device wafer.

2. The method as in claim 1, wherein the support wafer is made of silicon and the gaseous etchant is XeF₂.

3. The method as in claim 2, wherein the carrier passivation layer in the carrier wafer and the passivation layer on the device wafer are silicon oxide.

4. The method as in claim 2, wherein the carrier passivation layer is about 100 angstroms.

5. The method as in claim 2, wherein the membrane is less than one micron in thickness.

6. The method as in claim 2, wherein the membrane is silicon.

7. The method as in claim 2, wherein the membrane is made of a material other than silicon.

8. The method as in claim 1, further comprising:

forming a through hole through the device wafer to connect the surface of the device wafer and an opposing surface of the device wafer; and

bonding a back wafer to the opposing surface of the device wafer to cover the through hole.

9. The method as in claim 8, further comprising patterning the back wafer to have a sealing pattern around the through hole to seal the through hole.

10. The method as in claim 9, further comprising:

after the removal of the carrier passivation layer, patterning the back wafer to expose the through hole through the back wafer.

21. The method as in claim 20, wherein the posts are metals.

22. The methods as in claim 20, wherein the posts are silicon.

23. The method as in claim 20, wherein the membrane is a metal.

24. The method as in claim 20, wherein the membrane is a material different from silicon.

23-1. The method as in claim 20, wherein the membrane is a polymer.