Memory system allowing fast operation of processor while using flash memory incapable of random access

• US 20040064606A1
• Filed: 02/25/2003
• Published: 04/01/2004
• Est. Priority Date: 09/26/2002
• Status: Active Grant

• Current Assignee: Acacia Research Group LLC (Acacia Research Corporation)
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Kimura, Masatoshi
• Granted Patent: US 6,810,444 B2
• Time in Patent Office: Days
• US Class Current: 710/56
• CPC Class Codes: G06F 13/4239 with asynchronous protocol

Abstract

A DMA control circuit controls DMA transfer between a flash memory and a main memory. An S/P bus conversion circuit converts serial data output from the flash memory into parallel data and outputs the parallel data to the main memory. This eliminates the need for the CPU downloading file data from the flash memory to the main memory, allowing connection of a non-volatile memory with a large capacity, without reduction in the processing speed of the system.

Claims

1. A memory system, comprising:

a non-volatile memory;

a main memory connected to an external bus to which a processor is connected;

a transfer control portion controlling direct memory access transfer between said non-volatile memory and said main memory; and

a bus conversion portion performing conversion between parallel data and serial data between said non-volatile memory and said main memory.

2. The memory system according to claim 1, wherein

said main memory includes a plurality of main memories,

said memory system further comprises a bus switch portion switching a bus such that a second main memory different from a first main memory is connected to said non-volatile memory via said bus conversion portion if said first main memory is connected to said external bus, and that said first main memory is connected to said non-volatile memory via said bus conversion portion if said second main memory is connected to said external bus.

3. The memory system according to claim 2, wherein said bus switch portion connects both said first main memory and said second main memory to said external bus, and disconnects both said first main memory and said second main memory from said bus conversion portion.

4. The memory system according to claim 2, further comprising a control signal generation portion connected to said external bus and interpreting a command received from said processor to control said transfer control portion and said bus switch portion.

5. The memory system according to claim 2, further comprising an output portion receiving a signal indicating a bus switch state by said bus switch portion and outputting the signal to said processor via said external bus.

6. The memory system according to claim 5, wherein said output portion receives a signal indicating that direct memory access transfer by said transfer control portion is terminated and outputting the signal to said processor via said external bus.

7. The memory system according to claim 4, wherein at least said transfer control portion, said bus conversion portion, said bus switch portion and said control signal generation portion are formed on one chip.

8. The memory system according to claim 7, wherein at least said one chip and said plurality of main memories are integrated into said processor.