Structure and method of cache memory data update

• US 20040064644A1
• Filed: 04/28/2003
• Published: 04/01/2004
• Est. Priority Date: 09/30/2002
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Chen, Wei-Pin, Lin, Patrick
• Granted Patent: US 7,114,031 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0808 with cache invalidating means G06F12/0815 takes precedence

Abstract

The present invention relates to a structure and a method of data update in a cache memory inside a local processor, which uses the feature of cache control. A buffer block of a header buffer is mapped to a memory space at several different address sectors addressed by the local processor. Whenever the local processor attempts to access the internal cache memory, cache missing will occur so that a local processor will be forced to alternatively request new data from buffer blocks of a header buffer in a HCA. Consequently, the whole block is loaded into cache memory. This does not only boost cache update performance but also accelerates packet access.

Claims

1. A structure of cache memory data update applied to a cache system of a local processor to access data received from a host channel adapter (HCA), which allows a host processor to link to Infiniband, comprising:

a buffer memory to store received data temporarily and to be divided into several buffer blocks;

a cache memory embedded in the local processor and addressed to the buffer blocks by mapping a memory space; and

a data loading mechanism that maps each said buffer block to the memory space at several address sectors, whereby the local processor is addressing the address sectors with respect to said buffer block, then a condition of cache missing occurs so that data of said buffer block is loaded to update data in the cache memory.

2. The structure of claim 1, wherein the data received by said buffer memory is a packet header.

3. The structure of claim 1, wherein said buffer blocks on said buffer memory is mapped to said memory space in turn.

4. The structure of claim 3, wherein said local processor addresses the address sectors in said memory space in order so as to cause cache missing on the cache memory to load updated data from the buffer blocks.

5. A structure of cache memory data updating applied to a cache system of a processor, comprising:

an external memory to store received data temporarily and to be divided into several buffer blocks;

a cache memory embedded in said local processor and mapped to said buffer blocks by addressing of a memory space; and

a data loading mechanism that maps each said buffer block to said memory space in turn, wherein said processor addresses the addresses of said memory space in order so as to cause cache missing to load updated data from said buffer blocks.

6. The structure of claim 5, wherein the data in said buffer blocks of said external memory is compulsively mapped to said memory space at several different address sectors.

7. The structure of claim 6, wherein said processor reads addresses with respect to said buffer blocks so as to cause cache missing to load updated data from said buffer blocks.

8. A method of cache memory data updating applied to a cache system of a processor, comprising the steps of:

dividing an external memory of said processor into several buffer blocks to store temporarily data received by the processor;

addressing different addresses in a memory space to the same buffer block in said external memory; and

when the processor is addressing said different addresses, cache missing in the cache system occurs so as to load into the same buffer block in said external memory according to the addressing of said addresses, thereby obtaining updated data of said buffer blocks in said cache system.

9. A method of cache memory data updating applied to the cache system of a processor, comprising the steps of:

dividing an external memory into several buffer blocks to save temporarily data received by the processor;

mapping said buffer blocks to certain memory space in turn; and

when the processor is reading the memory space, cache missing in the cache system occurs so as to load the data in said buffer blocks in turn, thereby obtaining updated data of the buffer blocks.

10. A method of cache memory data updating applied to cache memory of a processor, comprising the steps of:

dividing an external memory into several buffer blocks to save temporarily data received by the processor;

mapping said buffer blocks in turn to a memory space with an address range and said cache memory capable of addressing the address range; and

when the processor addressing said address range, cache missing occurring so that data in said buffer blocks is alternatively loaded to obtain updated data of the buffer blocks.