Method of operating a memory at high speed using a cycle ready status output signal

• US 20040064661A1
• Filed: 09/16/2003
• Published: 04/01/2004
• Est. Priority Date: 09/16/2002
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Agrawal, Vikas K., Sheffield, Bryan D., Badi, Eric L., Spriggs, Stephen W.
• Granted Patent: US 7,200,730 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Claims

1. A method of operating a memory at a maximum rate, comprising:

initiating a memory operation;

identifying a completion of the memory operation;

generating a cycle ready strobe signal upon the identified completion; and

employing the cycle ready strobe signal for initiation of a next memory operation.

2. The method of claim 1, wherein the memory operation comprises a read operation.

3. The method of claim 1, wherein initiating a memory operation comprises:

inputting a clock strobe signal associated with a system clock signal into a memory control circuit operable to generate one or more memory control signals upon receipt of the clock strobe signal.

4. The method of claim 3, wherein one of the control signals comprises a bit line precharge enable signal, and wherein generating the cycle ready strobe signal comprises activating a cycle ready circuit when the bit line precharge enable signal transition to indicate initiation of a bit line precharge operation.

5. The method of claim 4, wherein activating the cycle ready circuit causes the cycle ready circuit to generate the cycle ready strobe signal a predetermined time after the bit line precharge enable signal transition.

6. The method of claim 5, wherein the predetermined time is sufficient to ensure that one or more true and complement bit line pairs substantially equalize and reach a predetermined precharge level.

7. The method of claim 6, wherein the predetermined time varies with respect to at least one of voltage, temperature and process condition variations.

8. The method of claim 7, wherein the variation in the predetermined time correlates substantially with a variation in time for the one or more true and complement bit line pairs substantially equalize and reach the predetermined precharge level due to variations in one or more of voltage, temperature and process conditions.

9. The method of claim 1, wherein employing the cycle ready strobe signal for initiation of the next memory operation comprises:

identifying the generation of the cycle ready strobe signal;

modifying a multiplexer input select control signal in response thereto;

feeding a memory multiplexer logic circuit with both the clock strobe signal and the cycle ready strobe signal; and

using the modified multiplexer input select control signal to pass the cycle ready strobe signal to a memory control circuit to generate one or more memory control signals for initiating the next memory operation.

10. The method of claim 1, wherein identifying the completion of the memory operation comprises detecting a bit line precharge enable signal transition indicating an initiation of a bit line precharge process.

11. A method of operating a memory, comprising:

initiating a first memory operation with an input clock signal associated with a system clock;

generating a cycle ready strobe signal upon a completion of the memory operation; and

using the cycle ready strobe signal to initiate a next memory operation.

12. The method of claim 11, wherein the cycle ready strobe signal transitions to enable initiation of the next memory operation a predetermined period of time after the completion of the memory operation.

13. The method of claim 12, further comprising identifying the completion of the memory operation by identifying a transition of a bit line precharge enable signal, wherein the transition indicates an initiation of a bit line precharge process.

14. The method of claim 13, wherein the predetermined period of time is sufficient to ensure that one or more true and complement bit line pairs substantially equalize and reach a predetermined precharge level.

15. The method of claim 14, wherein the predetermined time period varies with respect to at least one of voltage, temperature and process condition variations.

16. The method of claim 15, wherein the variation in the predetermined time period correlates substantially with a variation in time for the one or more true and complement bit line pairs substantially equalize and reach the predetermined precharge level due to variations in one or more of voltage, temperature and process conditions.

17. The method of claim 11, wherein initiating a first memory operation with the input clock strobe signal or the next memory operation with the cycle ready strobe signal comprises:

triggering a transition of an internal memory clock signal;

transitioning a bit line precharge signal to disable a bit line precharge operation based on the transition of the internal memory clock signal;

enabling selected row and column decoder circuitry for addressing one or more selected memory cells within the memory based on the transition of the internal memory clock signal;

initiating a tracking circuit that waits a predetermined tracking time associated with a time needed for selected true and complementary bit lines associated with the one or more selected memory cells to establish a voltage differential therebetween based on a state of the one ore more selected memory cells, the initiation of the tracking circuit based on the transition of the internal memory clock signal; and

outputting a reset signal from the tracking circuit after the predetermined tracking time, thereby disabling the internal memory clock signal, and initiating a bit line precharge operation.