Method and apparatus for controlling the rate at which instructions are executed by a microprocessor system

• US 20040064745A1
• Filed: 09/26/2002
• Published: 04/01/2004
• Est. Priority Date: 09/26/2002
• Status: Abandoned Application

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Kadambi, Sudarshan
• Application Number:
  US10/259,720
• Publication Number:
  US 20040064745A1
• Time in Patent Office: Days
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

One embodiment of the present invention provides a system that facilitates controlling the rate at which instructions are executed by a microprocessor. The system starts by receiving a signal indicating the existence of a throttling condition. In response to the throttling condition, the system reduces the rate at which instructions are executed by the microprocessor. In a variation on this embodiment, the throttling condition can include a processor idle state, a processor overheating state, or a power over-consumption state.

Claims

1. A method for throttling a microprocessor comprising:

receiving a signal indicating the existence of a throttling condition; and

in response to the throttling condition, performing the throttling by reducing the rate at which instructions are executed by the microprocessor.

2. The method of claim 1, wherein prior to performing the throttling, the method further involves determining a rate at which instructions are to be executed by the microprocessor during the existence of the throttling condition.

3. The method of claim 1, wherein receiving the signal indicating the existence of the throttling condition further involves receiving the signal from a service processor.

4. The method of claim 1, wherein receiving the signal indicating the existence of the throttling condition further involves receiving the signal from an operating system.

5. The method of claim 1, wherein receiving the signal indicating the existence of the throttling condition further involves receiving the signal from a sensor on the microprocessor.

6. The method of claim 5, wherein the sensor on the microprocessor detects the temperature of the microprocessor.

7. The method of claim 1, wherein reducing the rate at which instructions are executed by the microprocessor further involves modifying an instruction dispatch policy so that the number of instructions being dispatched per clock cycle is less than the number of functional units within the microprocessor that are able to receive an instruction in a given clock cycle.

8. The method of claim 1, wherein reducing the rate at which instructions are executed by the microprocessor further involves waiting a predetermined number of clock cycles between each instruction fetch operation.

9. The method of claim 1, wherein reducing the rate at which instructions are executed by the microprocessor further involves reducing the internal clock frequency of the microprocessor.

10. The method of claim 1, wherein the throttling condition can include:

a processor idle state;

a processor overheating state; and

a power over-consumption state.

11. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for throttling a microprocessor comprising:

receiving a signal indicating the existence of a throttling condition; and

in response to the throttling condition, performing the throttling by reducing the rate at which instructions are executed by the microprocessor.

12. The computer-readable storage medium of claim 11, wherein prior to performing the throttling, the method further involves determining a rate at which instructions are to be executed by the microprocessor during the existence of the throttling condition.

13. The computer-readable storage medium of claim 11, wherein receiving the signal indicating the existence of the throttling condition further involves receiving the signal from a service processor.

14. The computer-readable storage medium of claim 11, wherein receiving the signal indicating the existence of the throttling condition further involves receiving the signal from an operating system.

15. The computer-readable storage medium of claim 11, wherein receiving the signal indicating the existence of the throttling condition further involves receiving the signal from a sensor on the microprocessor.

16. The computer-readable storage medium of claim 15, wherein the sensor on the microprocessor detects the temperature of the microprocessor.

17. The computer-readable storage medium of claim 11, wherein reducing the rate at which instructions are executed by the microprocessor further involves modifying an instruction dispatch policy so that the number of instructions being dispatched per clock cycle is less than the number of functional units within the microprocessor that are able to receive an instruction in a given clock cycle.

18. The computer-readable storage medium of claim 11, wherein reducing the rate at which instructions are executed by the microprocessor further involves waiting a pre-determined number of clock cycles between each instruction fetch operation.

19. The computer-readable storage medium of claim 11, wherein reducing the rate at which instructions are executed by the microprocessor further involves reducing the internal clock frequency of the microprocessor.

20. The computer-readable storage medium of claim 11, wherein the throttling condition can include:

a processor idle state;

a processor overheating state; and

a power over-consumption state.

21. An apparatus for throttling a microprocessor comprising:

a receiving mechanism configured to receive a signal indicating the existence of a throttling condition; and

a throttling mechanism configured to perform the throttling by reducing the rate at which instructions are executed by the microprocessor.

22. The apparatus of claim 21, further comprising a determination mechanism configured to determine a rate at which instructions are to be executed by the microprocessor during the existence of the throttling condition.

23. The apparatus of claim 21, wherein the receiving mechanism is additionally configured to receive the signal from a service processor.

24. The apparatus of claim 21, wherein the receiving mechanism is additionally configured to receive the signal from an operating system.

25. The apparatus of claim 21, wherein the receiving mechanism is additionally configured to receive the signal from a sensor on the microprocessor.

26. The apparatus of claim 25, wherein the sensor on the microprocessor detects the temperature of the microprocessor.

27. The apparatus of claim 21, wherein the throttling mechanism is additionally configured to modify an instruction dispatch policy so that the number of instructions being dispatched per clock cycle is less than the number of functional units within the microprocessor that are able to receive an instruction in a given clock cycle.

28. The apparatus of claim 21, wherein the throttling mechanism is additionally configured to wait a pre-determined number of clock cycles between each instruction fetch operation.

29. The apparatus of claim 21, the throttling mechanism is additionally configured to reduce the internal clock frequency of the microprocessor.

30. The apparatus of claim 21, wherein the throttling condition can include:

a processor idle state;

a processor overheating state; and

a power over-consumption state.