REDUCED LATENCY INTERLEAVER UTILIZING SHORTENED FIRST CODEWORD

• US 20040064782A1
• Filed: 01/04/2002
• Published: 04/01/2004
• Est. Priority Date: 01/04/2002
• Status: Active Grant

• Current Assignee: Yitran Communications Ltd. (Allalouf Capital Ltd.)
• Original Assignee: Yitran Technologies Ltd.
• Inventors: Lerner, Gregory, Raphaeli, Dan, Kaufman, Oren, Zarud, Boris
• Granted Patent: US 6,718,503 B1
• Time in Patent Office: Days
• US Class Current: 714/800
• CPC Class Codes: H03M 13/2757 Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
• CPC Class Codes: H04B 2203/5408 using protocols
• CPC Class Codes: H04B 3/542 the information being in digital form

Abstract

A novel and useful interleaver/de-interleaver mechanism for reducing the latency of transmitted interleaved codewords. The interleaver/de-interleaver mechanism utilizes a shortened first codeword which functions to offset the interleaving and transmission of subsequent codewords so as to achieve reduced latency depending on the degree of shortening applied. The interleaver/de-interleaver mechanism is particularly useful in power line carrier based systems to reduce the exposure to burst errors by providing interleaving with minimal latency penalty.

Claims

1. A method of interleaving a stream of codewords, each codeword having a length L symbols, said method comprising the steps of:

interleaving the last L-U symbols of a first codeword with the first L-U symbols of a second codeword;

interleaving the first U symbols of a third codeword with the last U symbols of said second codeword;

shortening the initial first codeword received in said stream of codewords by skipping over the first U symbols of said initial first codeword; and

wherein L and U are positive integers.

2. The method according to claim 1, wherein said codeword length L is equal to 9 and comprises 7 data symbols and 2 parity symbols.

3. The method according to claim 1, wherein U is equal to 4 data symbols.

4. The method according to claim 1, wherein said codeword length L is equal to 7 and comprises 5 data symbols and 2 parity symbols.

5. The method according to claim 1, wherein U is equal to 1 data symbol.

6. The method according to claim 1, wherein said method is implemented in an Application Specific Integrated Circuit (ASIC).

7. The method according to claim 1, wherein said method is implemented in a Field Programmable Gate Array (FPGA).

8. An interleaver for interleaving a stream of codewords, each codeword having a length L symbols, said method comprising the steps of:

means for dividing a beginning codeword into a first portion and a second portion;

means for dividing an ending codeword into a first portion and a second portion;

means for interleaving said second part of said beginning codeword and said first part of said ending codeword with one or more intermediate codewords; and

means for skipping the first portion of an initial codeword received in said stream of codewords.

9. The interleaver according to claim 8, wherein said means for interleaving comprises a 2:

1 interleaver.

10. The interleaver according to claim 8, wherein said codeword comprises 7 data symbols and 2 parity symbols.

11. The interleaver according to claim 8, wherein said codeword comprises 5 data symbols and 2 parity symbols.

12. The interleaver according to claim 8, wherein said first portion of said beginning codeword and of said ending code work comprises 4 data symbols.

13. The interleaver according to claim 8, wherein said first portion of said beginning codeword and of said ending code work comprises 1 data symbol.

14. The interleaver according to claim 8, wherein said second portion of said beginning codeword and of said ending code work comprises 3 data symbols and 2 parity symbols.

15. The interleaver according to claim 8, wherein said second portion of said beginning codeword and of said ending code work comprises 4 data symbol and 2 parity symbols.

16. The method according to claim 8, wherein said method is implemented in an Application Specific Integrated Circuit (ASIC).

17. The method according to claim 8, wherein said method is implemented in a Field Programmable Gate Array (FPGA).

18. An interleaver for interleaving a stream of codewords, each codeword having a length L symbols, said method comprising the steps of:

means for interleaving the last L-U symbols of a first codeword with the first L-U symbols of a second codeword;

means for interleaving the first U symbols of a third codeword with the last U symbols of said second codeword;

means for shortening the initial first codeword received in said stream of codewords by discarding the first U symbols of said initial first codeword; and

wherein L and U are positive integers.

19. The interleaver according to claim 18, wherein said codeword length L is equal to 9 and comprises 7 data symbols and 2 parity symbols.

20. The interleaver according to claim 18, wherein U is equal to 4.

21. The interleaver according to claim 18, wherein said codeword length L is equal to 7 and comprises 5 data symbols and 2 parity symbols.

22. The interleaver according to claim 18, wherein U is equal to 1.

23. The interleaver according to claim 18 adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

24. The interleaver according to claim 18 adapted to be implemented in a Field Programmable Gate Array (FPGA).

25. A method of de-interleaving a stream of symbols, said method comprising the steps of:

sequentially counting each received symbol;

upon receipt of the first L symbols, de-interleaving and extracting L-U symbols to construct a first shortened codeword; and

upon receipt of each subsequent L symbols, de-interleaving and extracting L symbols to construct subsequent codewords.

26. The method according to claim 25, further comprising the step of inserting predetermined dummy symbols to the beginning of said first shortened codeword to yield an L symbol first codeword.

27. The method according to claim 26, further comprising decoding said L symbol first codeword so as to yield packet header information and Cyclic Redundancy Code (CRC) information corresponding thereto.

28. The method according to claim 25, wherein said codeword length L is equal to 9 and comprises 7 data symbols and 2 parity symbols.

29. The method according to claim 25 wherein U is equal to 4 data symbols.

30. The method according to claim 25, wherein said codeword length L is equal to 7 and comprises 5 data symbols and 2 parity symbols.

31. The method according to claim 25, wherein U is equal to 1 data symbol.

32. The method according to claim 25, wherein said method is implemented in an Application Specific Integrated Circuit (ASIC).

33. The method according to claim 25, wherein said method is implemented in a Field Programmable Gate Array (FPGA).

34. A de-interleaver for de-interleaving a stream of symbols, said method comprising the steps of:

means for sequentially counting each received symbol;

means for de-interleaving the first L symbols and for extracting L-U symbols therefrom so as to construct a first shortened codeword; and

means for de-interleaving subsequent groups of L symbols and for extracting L symbols from the previously received group of 2L symbols so as to construct subsequent codewords.

35. The de-interleaver according to claim 34 adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

36. The de-interleaver according to claim 34 adapted to be implemented in a Field Programmable Gate Array (FPGA).

37. A modem transceiver for transmitting and receiving signals a shared communications media based network, comprising:

a coupling circuit for generating a receive signal received over said network and for outputting a transmit signal onto said network;

a transmitter adapted to modulate data to be transmitted in accordance with a modulation scheme so as to generate a transmit waveform therefrom, said transmitter comprising an interleaver for interleaving a stream of codewords, each codeword having a length L symbols, said interleaver comprising;

means for interleaving the last L-U symbols of a first codeword with the first L-U symbols of a second codeword;

means for interleaving the first U symbols of a third codeword with the last U symbols of said second codeword;

means for shortening the initial first codeword received in said stream of codewords by discarding the first U symbols of said initial first codeword;

wherein L and U are positive integers;

a receiver adapted to demodulate said receive signal in accordance with said modulation scheme so as to generate a receive data signal therefrom, said receive comprising a de-interleaver for de-interleaving a stream of symbols, said de-interleaver comprising;

means for sequentially counting each received symbol;

means for de-interleaving the first L symbols and for extracting L-U symbols therefrom so as to construct a first shortened codeword;

means for de-interleaving subsequent groups of L symbols and for extracting L symbols from the previously received group of 2L symbols so as to construct subsequent codewords;

a media access control (MAC) circuit adapted to interface an application processor to said shared communications media;

said application processor adapted to control the operation of said transmitter, receiver and MAC and to provide an interface between said MAC and an external host.

38. The modem according to claim 37, wherein said modulation scheme comprises code shift keying (CSK) modulation.

39. The modem according to claim 37, wherein said codeword length has a length L equal to 9 and comprises 7 data symbols and 2 parity symbols.

40. The modem according to claim 37, wherein U is equal to 4.

41. The modem according to claim 37, wherein said codeword length has a length L equal to 7 and comprises 5 data symbols and 2 parity symbols.

42. The modem according to claim 37, wherein U is equal to 1.

43. The modem according to claim 37 adapted to be implemented in an Application Specific Integrated Circuit (ASIC).

44. The modem according to claim 37 adapted to be implemented in a Field Programmable Gate Array (FPGA).