Hardened voyage data recorder
First Claim
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1. A hardened voyage data recorder, comprising:
- (a) a removable memory subsystem;
(b) a mounting base subsystem removably coupled to said memory subsystem, wherein said mounting base subsystem protects and includes therein electronic circuits for electronically accessing said memory subsystem.
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Abstract
A hardened voyage data recorder includes two subsystems: a removable non-volatile memory and a base containing electronics and firmware for communicating with data sensing systems and for accessing the memory. According to the invention, the memory is protected in a “boiler” and the electronics includes an ETHERNET interface for connecting to shipboard data acquisition devices. The firmware is preferably configured via web pages. A communications protocol for communicating with the recorder is also disclosed.
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Citations
34 Claims
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1. A hardened voyage data recorder, comprising:
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(a) a removable memory subsystem;
(b) a mounting base subsystem removably coupled to said memory subsystem, wherein said mounting base subsystem protects and includes therein electronic circuits for electronically accessing said memory subsystem. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A hardened voyage data recorder, comprising:
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(a) a removable memory subsystem; and
(b) a mounting base subsystem removably coupled to said memory subsystem, wherein said removable memory subsystem includes non-volatile memory enclosed within a boiler, and said mounting base subsystem is adapted to be mounted on the exterior of a marine vessel. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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19. A hardened voyage data recorder, comprising:
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(a) a removable memory subsystem;
(b) a mounting base subsystem removably coupled to said memory subsystem; and
(c) at least one memory interface converter chip coupled to said removable memory subsystem. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26)
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27. A hardened voyage data recorder, comprising:
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(a) a removable memory subsystem, wherein said removable memory subsystem includes a stacked memory and a plurality of memory interface chips arranged for communication with a processor such that a large number of memory chips may be driven; and
(b) a mounting base subsystem removably coupled to said memory subsystem. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34)
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Specification