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Flash memory cells with separated self-aligned select and erase gates, and process of fabrication

  • US 20040065917A1
  • Filed: 10/07/2002
  • Published: 04/08/2004
  • Est. Priority Date: 10/07/2002
  • Status: Active Grant
First Claim
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1. A flash memory cell array, comprising:

  • a substrate, a source diffusion in the substrate, vertically stacked pairs of floating gates and control gates on opposite sides of the source diffusion, an erase gate directly above the source diffusion and between the stacked gates, select gates on the sides of the stacked gates opposite the erase gate, programming paths from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extending from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate.

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