Flash memory cells with separated self-aligned select and erase gates, and process of fabrication

• US 20040065917A1
• Filed: 10/07/2002
• Published: 04/08/2004
• Est. Priority Date: 10/07/2002
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Actrans Systems Inc. (Microchip Technology Incorporated)
• Inventors: Tuntasood, Prateep, Fan, Der-Tsyr, Chen, Chiou-Feng
• Granted Patent: US 6,747,310 B2
• Time in Patent Office: Days
• US Class Current: 257/315
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

Flash memory and process of fabrication in which vertically stacked pairs of floating gates and control gates are formed on opposite sides of a source diffusion in a substrate, an erase gate is formed directly above the source diffusion and between the stacked gates, select gates are formed on the sides of the stacked gates opposite the erase gate, programming paths extend from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extend from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate. In some embodiments, the source regions are connected electrically to the erase gates, and in others the floating gates project laterally beyond the control gates on one or both sides of the control gates. These memory cells are very small in size and provide substantially better programming and erase performance than memory cells of the prior art.

Claims

1. A flash memory cell array, comprising:

a substrate, a source diffusion in the substrate, vertically stacked pairs of floating gates and control gates on opposite sides of the source diffusion, an erase gate directly above the source diffusion and between the stacked gates, select gates on the sides of the stacked gates opposite the erase gate, programming paths from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extending from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate.

2. The flash memory cell array of claim 1 wherein the erase gate and the source diffusion are connected together electrically.

3. The flash memory cell array of claim 1 wherein the floating gates extend laterally beyond the control gates toward the erase gate.

4. The flash memory cell array of claim 3 wherein the floating gates extend up to 500 Å

beyond the control gates.

5. The flash memory cell array of claim 1 wherein the floating gates are relatively thin and have rounded side edges.

6. The flash memory cell array of claim 1 wherein the floating gates have a thickness on the order of 100 Å

-700 Å

.

7. The flash memory cell array of claim 1 including a tunneling dielectric having a thickness on the order of 200 Å

-1000 Å

between the edge portions of the floating gates and the erase gate.

8. The flash memory cell array of claim 7 wherein the tunneling dielectric is selected from the group consisting of CVD silicon oxide, thermally grown silicon oxide, and combinations thereof.

9. The flash memory cell array of claim 1 including a dielectric cap having a thickness on the order of 1000 Å

-3000 Å

above each of the control gates.

10. The flash memory cell array of claim 9 wherein the dielectric is selected from the group consisting of CVD silicon oxide, thermally grown silicon oxide, and combinations thereof.

11. The flash memory cell array of claim 1 wherein the source diffusion and the erase gate are self-aligned with the stacked pairs of floating gates and control gates between which they are positioned.

12. The flash memory cell array of claim 1 including a bit line diffusion in the substrate between two adjacent select gates.

13. The flash memory cell array of claim 1 including a select gate oxide having a thickness of 10 Å

-200 Å

which is used for programming and reading.

14. The flash memory cell array of claim 1 including an erase gate oxide having a thickness on the order of 10 Å

-500 Å

.

15. The flash memory cell array of claim 1 wherein the source diffusion, the erase gate, and the mid-channel region can be independently biased or electrically connected together for selectively controlling electron migration from the floating gate to the source diffusion, the erase gate, and the channel region.

16. The flash memory cell array of claim 1 including dielectric spacers on the side walls of the control gates.

17. The flash memory cell array of claim 16 wherein the dielectric spacers are fabricated of a dielectric material selected from the group consisting of CVD silicon oxide, CVD silicon nitride, thermally grown silicon oxide, and the combination thereof.

22. The flash memory cell array of claim 1 wherein the inter-poly tunnel oxide between the floating gate and the erase gate has a thickness on the order of 200 Å

-1000 Å and

is selected from the group consisting of CVD silicon oxide, thermally grown silicon oxide, and combinations thereof.

18. A flash memory cell array, comprising:

a substrate, an tunnel oxide formed on the substrate, a relatively thin floating gate positioned above the tunnel oxide, a control gate which is substantially thicker than the floating gate positioned above and in vertical alignment with the floating gate, a relatively thick dielectric cap on top of the control gate, dielectric spacers on opposite sides of the control gate, a dielectric between the control gate and the floating gate, a select gate and an erase gate on opposite sides of the floating gate and the control gate extending at least part way up the dielectric spacers on the control gate but not extending above the dielectric cap on top of the control gate, gate oxides beneath the select gate and the erase gate, a doped drain diffusion in the substrate adjacent to the select gate, a doped source diffusion in the substrate beneath the erase gate, an inter-poly tunnel oxide between a side edge of the floating gate and the erase gate, an electron tunneling path for electron migration out of floating gate during erase operations through at least one of the tunnel oxides to at least one of the source diffusion and the erase gate, and a hot carrier injection path for injecting electrons into the floating gate during programming operations extending from a channel region between the select gate and the floating gate through the tunnel oxide on the substrate to the floating gate, the electron tunneling path and the hot electron injection path being separately located on opposite sides of the floating gate.

19. The flash memory cell array of claim 18 wherein the floating gate has a thickness on the order of 100 Å

-700 Å

.

20. The flash memory cell array of claim 18 wherein the floating gate and control gate have vertically aligned side walls.

21. The flash memory cell array of claim 18 wherein the floating gate has a rounded side wall and extends laterally up to about 500 Å

beyond control gate toward the erase gate.

23. The flash memory cell array of claim 18 wherein the spacer between the control gate and the erase gate has a thickness on the order of 200 Å

-1000 Å and

is selected from the group consisting of CVD silicon oxide, CVD silicon nitride, thermally grown silicon oxide, and combinations thereof.

24. The flash memory cell array of claim 18 wherein the dielectric cap on top of the control gate has a thickness on the order of 1000 Å

-3000 Å and

is fabricated of a dielectric selected from the group consisting of CVD silicon oxide, CVD silicon nitride, thermally grown silicon oxide, and combinations thereof.

25. The flash memory cell array of claim 18 wherein the source diffusion and the erase gate are self-aligned with the floating gate and the control gate.

26. The flash memory cell array of claim 18 including a bit line diffusion in the substrate and self-aligned with the floating gate and the control gate.

27. The flash memory cell array of claim 18 wherein oxide beneath the select gate oxide has a thickness of on the order of 10 Å

-200 Å and

is used for programming and reading operations.

28. The flash memory cell array of claim 18 wherein the source diffusion and the erase gate can be can be independently biased or electrically connected together for selectively controlling electron migration from the floating gate to the source diffusion and the erase gate.

29. The flash memory cell array of claim 18 wherein the erase gate oxide has a thickness on the order of 10 Å

-500 Å and

is used for erase operations.

30. The flash memory cell array of claim 18 wherein the source diffusion, the erase gate, and the mid-channel region can be independently biased or electrically connected together for selectively controlling electron migration from the floating gate to the source diffusion, the erase gate, and the channel region.

31. The flash memory cell array of claim 18 wherein the dielectric spacers on the control gate are fabricated of a material selected from the group consisting of CVD silicon oxide, CVD silicon nitride, thermally grown silicon oxide, and combinations thereof.

32. A process of fabricating a flash memory cell array, comprising the steps of:

forming an oxide layer on a substrate, forming a first silicon layer on the oxide layer;

forming a dielectric film on the first silicon layer;

forming a second silicon layer on the dielectric film;

removing portions of the second silicon layer to form a plurality of control gates with exposed side walls;

forming dielectric spacers on the side walls of the control gates;

using the dielectric spacers as a mask, anisotropically etching away portions of the dielectric film, the oxide layer and the first silicon layer to form floating gates which are self-aligned with and of greater lateral extent than the control gates;

forming source diffusions in the substrate between adjacent ones of the floating gates;

forming erase gates above the source diffusions and select gates on opposite sides of the control and floating gates from the erase gates;

forming a drain diffusion in the substrate between adjacent ones of the select gates; and

forming a bit line above the gates and a bit line contact which interconnects the bit line and the drain diffusion.

33. The process of claim 32 wherein the erase gates and select gates are formed by depositing a third silicon layer over the control gates and the substrate, and removing portions of the third silicon layer above the control gates.

34. The process of claim 32 including the step of connecting one of the source diffusions and the erase gate above it together electrically.

35. The process of claim 32 wherein the first silicon layer and the floating gates are substantially thinner than the second silicon layer and the control gates.

36. The process of claim 35 including the step of rounding the side edges of the floating gates.

37. A process of fabricating a flash memory cell array, comprising the steps of:

forming an oxide layer on a substrate, forming a first silicon layer on the oxide layer;

forming a dielectric film on the first silicon layer;

forming a second silicon layer on the dielectric film;

removing portions of the second silicon layer to form a plurality of control gates with exposed side walls;

removing portions of the dielectric film and the first silicon layer between alternate pairs of the control gates;

forming dielectric spacers on the side walls of the control gates, with the spacers on the sides of the control gates where the dielectric film and the first silicon layer have been removed extending all the way to the oxide layer, and the spacers on the opposite sides of the control gates extending only to the dielectric film;

using the dielectric spacers which extend only to the dielectric film as a mask, anisotropically etching away the portions of the dielectric film and the first silicon layer between those spacers to form floating gates having portions which project laterally beyond the control gates on the side of the control gates where the spacers extend only to the dielectric film;

forming source diffusions in the substrate between the projecting portions of the floating gates;

forming erase gates above the source diffusions;

forming select gates on the sides of the control gates and floating gates where the spacers extend all the way to the oxide layer;

forming a drain diffusion in the substrate between adjacent ones of the select gates; and

forming a bit line above the gates and a bit line contact which interconnects the bit line and the drain diffusion.

38. The process of claim 37 wherein the erase gates and select gates are formed by depositing a third silicon layer over the control gates and the substrate, and removing portions of the third silicon layer above the control gates.

39. The process of claim 37 including the step of connecting one of the source diffusions and the erase gate above it together electrically.

40. The process of claim 37 wherein the first silicon layer and the floating gates are substantially thinner than the second silicon layer and the control gates.

41. The process of claim 40 including the step of rounding the side edges of the floating gates.

42. A process of fabricating a flash memory cell array, comprising the steps of:

forming an oxide layer on a substrate, forming a first silicon layer on the oxide layer;

forming a dielectric film on the first silicon layer;

forming a second silicon layer on the dielectric film;

removing portions of the second silicon layer, the dielectric film, and the first silicon layer to form a plurality of control gates and floating gates with exposed side walls, the floating gates being substantially thinner than the control gates;

oxidizing the control gates and the floating gates, with the control gates oxidizing at a faster rate than the thinner floating gates and more of the control gates being oxidized away, leaving the floating gates with portions which project laterally beyond the control gates;

forming source diffusions in the substrate between adjacent ones of the floating gates;

forming erase gates above the source diffusions;

forming select gates on opposite sides of the control and floating gates from the erase gates;

forming a drain diffusion in the substrate between adjacent ones of the select gates; and

forming a bit line above the gates and a bit line contact which interconnects the bit line and the drain diffusion.

43. The process of claim 42 wherein the erase gates and select gates are formed by depositing a third silicon layer over the control gates and the substrate, and removing portions of the third silicon layer above the control gates.

44. The process of claim 42 including the step of connecting one of the source diffusions and the erase gate above it together electrically.

45. The process of claim 42 wherein the side edges of the floating gates are rounded during the oxidization step.

46. The process of claim 42 wherein the oxidation is optimized to control oxide stress and edge rounding in the projecting edge portions of the floating gates.

47. A process of fabricating a flash memory cell array, comprising the steps of:

forming an oxide layer on a substrate, forming a first silicon layer on the oxide layer;

forming a dielectric film on the first silicon layer;

forming a second silicon layer on the dielectric film;

removing portions of the silicon layers and the dielectric film to form control gates and floating gates and, with the control gates overlying the floating gates and being separated from the floating gates by the dielectric film;

forming source diffusions in the substrate between adjacent ones of the floating gates;

depositing a third silicon layer on the control gates and exposed portions of the oxide layer; and

removing portions of the third silicon layer above the control gates to form erase gates above the source diffusions and select gates on the sides of the control gates opposite the erase gates.

48. The process of claim 47 wherein the floating gates are formed with portions which project laterally beyond the control gates toward the erase gates.

49. The process of claim 47 wherein the floating gates are formed with portions which project laterally beyond the control gates toward the select gates.

50. The process of claim 47 including the step of connecting one of the source regions and the erase gate above it together electrically.