Trench gate laterally diffused MOSFET devices and methods for making such devices

• US 20040065919A1
• Filed: 10/03/2002
• Published: 04/08/2004
• Est. Priority Date: 10/03/2002
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Wilson, Peter H., Thornton, Neill, Sapp, Steven
• Granted Patent: US 7,033,891 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A MOSFET device for RF applications that uses a trench gate in place of the lateral gate used in lateral MOSFET devices is described. The trench gate in the devices of the invention is provided with a single, short channel for high frequency gain. The device of the invention is also provided with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Such features allow these devices to maintain the advantages of the LDMOS structure (better linearity), thereby increasing the RF power gain. The trench gate LDMOS of the invention also reduces the hot carrier effects when compared to regular LDMOS devices by reducing the peak electric field and impact ionization. Thus, the devices of the invention will have a better breakdown capability.

Claims

1. A MOSFET device, comprising:

a trench gate structure containing an asymmetric insulating layer; and

a plurality of drift drain regions with a first drift region extending under the gate structure.

2. The device of claim 1, wherein the MOSFET device is a RF MOSFET device.

3. The device of claim 1, wherein the insulating layer comprises silicon oxide.

4. The device of claim 1, wherein the trench gate structure further comprises a single channel.

5. The device of claim 4, wherein the asymmetric insulating layer is thicker on the bottom of the trench than the side of the layer adjacent the single channel.

6. The device of claim 1, wherein the plurality of drift regions further comprises a second drift region.

7. The device of claim 6, wherein the second drift region has a dopant concentration higher than the first drift region.

8. The device of claim 1, further comprising a plurality of trench gate structures.

9. A RF MOSFET device, comprising:

a trench gate structure containing a single channel and an asymmetric oxide layer; and

a plurality of drift drain regions with a first drift region extending under the gate structure.

10. The device of claim 9, wherein the asymmetric oxide layer is thicker on the bottom of the trench than the side of the layer adjacent the single channel.

11. The device of claim 9, wherein the plurality of drift regions further comprises a second drift region with a dopant concentration higher than the first drift region.

12. A semiconductor device containing a MOSFET device comprising:

a trench gate structure containing a single channel and an asymmetric oxide layer; and

a plurality of drift drain regions with a first drift region extending under the gate structure.

13. The device of claim 12, wherein the asymmetric oxide layer is thicker on the bottom of the trench than the side of the layer adjacent the single channel.

14. The device of claim 12, wherein the plurality of drift regions further comprises a second drift region with a dopant concentration higher than the first drift region.

15. An electronic apparatus containing a MOSFET device comprising:

a trench gate structure containing a single channel and an asymmetric oxide layer that is thicker on the bottom of the trench than the side of the layer adjacent the single channel; and

a plurality of drift drain regions with a first drift region extending under the gate structure and a second drift region with a dopant concentration higher than the first drift region.

16. The apparatus of claim 15, wherein the asymmetric oxide layer is thicker on the bottom of the trench than the side of the layer adjacent the single channel.

17. The apparatus of claim 15, wherein the plurality of drift regions further comprises a second drift region with a dopant concentration higher than the first drift region.

18. A MOSFET device, comprising:

a trench gate structure containing an asymmetric insulating layer; and

a plurality of drift drain regions with a first drift region extending under the gate structure.

19. A method for making a MOSFET device, comprising:

providing a trench gate structure containing an asymmetric insulating layer; and

providing a plurality of drift drain regions with a first drift region extending under the gate structure.

20. The method of claim 19, wherein the MOSFET device is a RF MOSFET device.

21. The method of claim 19, including providing the insulating layer with a silicon oxide material.

22. The method of claim 19, including providing the trench gate structure with a single channel.

23. The method of claim 22, including making the asymmetric insulating layer thicker on the bottom of the trench relative than the side of the layer adjacent the single channel.

24. The method of claim 19, including providing the plurality of drift regions further with a second drift region having a dopant concentration higher than the first drift region.

25. A method for making a making a MOSFET device, comprising:

providing a substrate;

providing a trench in the substrate;

filling the trench with an insulating layer;

providing a second trench in the insulating layer such that the second trench is not symmetric relative to the first trench;

filling the second trench with a conductive material; and

providing a plurality of dopant regions adjacent the trench with a first dopant region extending under the trench.

26. The method of claim 25, including providing the substrate with an upper surface comprising an epitaxial layer.

27. The method of claim 26, further including providing the plurality of dopant regions within the epitaxial layer.

28. The method of claim 27, further including providing a second dopant region with a dopant concentration higher the first dopant region.

29. A method for making a making a MOSFET device, comprising:

providing a substrate having an epitaxial upper surface;

providing a trench in the upper surface;

filling the trench with an oxide layer;

providing a second trench in the oxide layer so that the second trench is not symmetric relative to the first trench;

filling the second trench with a conductive material; and

providing a plurality of dopant regions adjacent the trench and within the epitaxial layer, wherein the plurality of dopant regions contains a first dopant region extending under the trench and a second dopant region with a dopant concentration higher than the first dopant region.

30. A MOSFET device made the method comprising:

providing a substrate;

providing a trench in the substrate;

filling the trench with an insulating layer;

providing a second trench in the insulating layer such that the second trench is not symmetric relative to the first trench;

filling the second trench with a conductive material; and

providing a plurality of dopant regions adjacent the trench with a first dopant region extending under the trench.

31. A MOSFET device, comprising:

a trench gate structure containing an asymmetric insulating layer; and

a lateral drift region extending under the gate structure.

32. A MOSFET device, comprising:

a trench gate structure containing an insulating layer; and

a lateral drift region extending under the gate structure.