Display unit and drive system thereof and an information display unit

• US 20040066363A1
• Filed: 09/10/2003
• Published: 04/08/2004
• Est. Priority Date: 09/26/2000
• Status: Active Grant

• Current Assignee: Japan Display Central Incorporated (Japan Display Incorporated)
• Original Assignee: Toshiba Mobile Display Company Limited (Japan Display Incorporated)
• Inventors: Takahara, Hiroshi, Tsuge, Hitoshi, Yamano, Atsuhiro
• Granted Patent: US 7,737,933 B2
• Time in Patent Office: Days
• US Class Current: 345/98
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2310/0275 Details of drivers for data electrodes, other than drivers for liquid crystal, plasma or OLED displays, not related to handling digital grey scale data or to communication of data to the pixels by means of a current
• CPC Class Codes: G09G 2310/06 Details of flat display driving waveforms
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2320/0276 for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction
• CPC Class Codes: G09G 2320/041 Temperature compensation
• CPC Class Codes: G09G 2320/0606 Manual adjustment
• CPC Class Codes: G09G 2320/0626 for control of overall brightness
• CPC Class Codes: G09G 2320/0673 for control of gamma adjustment, e.g. selecting another gamma curve
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/2051 with use of a spatial dither pattern
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3625 using active addressing
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

In a display panel, a dummy pulse of a predetermined voltage signal is superimposed on a data signal and the dummy pulse has an amplitude much larger than the amplitude of the data signal, and thus a signal waveform applied to a light modulation layer such as LC layer is changed to a high frequency wave. The applying position of the dummy pulse is varied according to each color of R, G and B, or varied according to frame or field. By performing a MLS drive with the dummy pulse superimposed on the data signal, the amplitude difference between the selection signal and the data signal can be reduced. Thus, a common driver IC and a segment driver IC can be formed as one semiconductor chip to be placed on one side, constructing a three side free type.

Claims

1. A matrix type display unit having multiple scanning electrodes and multiple signal electrodes, comprising:

drive means including a scanning circuit to drive said scanning electrodes and a signal circuit to drive said signal electrodes, said drive means being positioned on one side of said display unit,

wherein a predetermined amplitude pulse is superimposed to a signal which is to be applied to said signal electrodes, in synchronization with one horizontal scanning period.

2. The display unit according to claim 1, wherein the scanning circuit and the signal circuit are formed within a single semiconductor chip.

3. The display unit according to claim 1, wherein by selecting simultaneously L number of the scanning electrodes where L is an integer greater than one, a gradation display is made.

9. An information display unit having the display unit according to claim 1 and an audio reception or transmission means.

4. A matrix type display unit having multiple scanning electrodes and multiple signal electrodes,

wherein a predetermined amplitude pulse is superimposed to a signal which is to be applied to said signal electrodes, in synchronization with one horizontal scanning period, and

wherein said pulse width is in a range from 0.06 to 0.23 when the horizontal scanning period is specified to be 1.

5. A matrix type display unit having multiple scanning electrodes and multiple signal electrodes, comprising

a pulse applying means for superimposing a predetermined amplitude pulse on a signal to be applied to each of said signal electrodes in synchronization with one horizontal scanning period;

and

a pulse control means for changing at least one of said pulse width and positions of said horizontal scanning period.

6. A driving method for a matrix type display unit having multiple scanning electrodes and multiple signal electrodes, comprising:

superimposing a predetermined amplitude pulse on a signal to be applied to each of said signal electrodes in synchronization with one horizontal scanning period, wherein said pulse is continuously applied during the horizontal scanning periods in odd-numbered and even-numbered order.

7. A driving method for a matrix type display unit having multiple scanning electrodes and multiple signal electrodes and having at least, a first pixel which modulates a first wavelength of light and a second pixel which modulates a second wavelength of light, said method comprising:

superimposing a predetermined amplitude pulse on a signal to be applied to each of said signal electrodes in synchronization with one horizontal scanning period, wherein a starting position of the horizontal scanning period of said pulse applied to said first pixel is different from a starting position of the horizontal scanning period of said pulse applied to said second pixel.

8. A driving method for a matrix type display unit having multiple scanning electrodes and multiple signal electrodes, comprising:

superimposing a predetermined amplitude pulse on a signal to be applied to said signal electrodes in synchronization with one horizontal scanning period, wherein by changing at least one of the pulse width and pulse amplitude, a display brightness of the display unit is varied.

10. A display unit comprising:

a scanning circuit selecting a scanning signal line;

a signal circuit having a RAM storing image data of one screen and applying a picture signal to a picture signal line; and

an image processing circuit for dither-processing or error-distribution processing of input image signals, wherein said image processing circuit transfers the resultant image data obtained by dither-processing or error-distribution processing to said RAM.

13. An information display unit comprising:

the display unit according to any one of claims 10, 11 and 12;

a receiver, and a loudspeaker.

15. The display unit according to claim 13, wherein the frame rate is varied respectively at the time of moving picture display and still-picture display.

11. A display unit displaying images by simultaneously selecting multi-scanning electrodes and through pulse-width modulation, comprising:

a segment driving circuit applying a signal to a segment signal line of said display unit; and

an image processing circuit generating image data processed by error distribution processing.

12. A liquid crystal display unit comprising:

a segment driver for driving a segment signal line;

a common driver for driving a common signal line;

a controller having a built-in image memory sufficient for at least one screen display, wherein said controller performs a first operation of dither-processing or error distribution processing of input image data and a second operation of transferring the resultant image data obtained by the dither processing or the error distribution processing to said built-in memory; and

operating means for switching between execution and non-execution of the error distribution processing or the dither-processing.

14. A driving method for a liquid crystal display unit achieving gradation display by frame rate control, wherein gradation data subject to the frame rate control comprise first gradation data and second gradation data;

the first gradation data being comprised of common divisors of 12;

the second gradation data being comprised of common divisors of 8;

conducting the gradation display for a still-picture, using said first gradation data and said second gradation data; and

conducting the gradation display for a moving picture, using said second gradation data.

16. A driving circuit for a display unit selecting simultaneously multiple common signal lines, comprising:

a gradation data shift circuit having multiple gradation registers and shifting said gradation registers; and

a gradation selection circuit formed in each segment signal line for selecting gradation data corresponding to image data based on the image data and the output data of said gradation data shift circuit;

wherein at least one of the gradation registers formed by data mirror-reversal in said gradation data shift circuit is omitted, and regarding the data of said omitted gradation registers, the data of the gradation data shift circuit is demodulated by reversing in said gradation selection circuit.

17. A driving method for a display unit selecting simultaneously multiple common signal lines, comprising:

shifting gradation data stored in registers by one frame or one field signal and one horizontal scanning signal; and

selecting gradation data corresponding to image data from said gradation data and image data through frame rate control using a processing circuit formed in each segment signal line;

wherein at least one gradation data generated by data mirror reversal in the gradation data of a gradation data shift circuit is omitted; and

wherein said omitted gradation data is identified by a polarity of the most significant bit of said image data and is demodulated by reversing the gradation data.

18. A driving circuit for a display unit selecting simultaneously multiple common signal lines, comprising:

a gradation data shift circuit having multiple gradation registers and shifting said gradation registers; and

a gradation selection circuit formed in each segment signal line for selecting gradation data corresponding to image data based on the image data and the output data of said gradation data shift circuit;

wherein at least one of the gradation registers formed by data mirror-reversal in said gradation data shift circuit is omitted, and regarding the data of said omitted gradation registers, the data of the gradation data shift circuit is demodulated by reversing in said gradation selection circuit, and

wherein the bit number of the gradation data stored in said gradation register is 12 or 8, or a common divisor of 12 or 8.

19. A matrix type display unit performing multiple gradation display through frame rate control;

wherein said display unit displays 16 gradations from 0 to 15 levels, and

in the case where the gradation level 0 is assigned to a black display and the gradation level 15 is assigned to a white display,

the level 1 indicates that a register length is 12, and one of said 12 is ON;

the level 2 indicates that a register length is 8, and one of said 8 is ON;

the level 3 indicates that a register length is 6, and one of said 6 is ON;

the level 4 indicates that a register length is 4, and one of said 4 is ON;

the level 5 indicates that a register length is 3, and one of said 3 is ON;

the level 6 indicates that a register length is 8, and three of said 8 are ON;

the level 7 indicates that a;

register length is 12, and five of said 12 are ON;

the level 8 indicates that a register length is 2, and one of said 2 is ON;

the level 9 indicates that a register length is 12, and seven of said 12 are ON;

the level 10 indicates that a register length is 3, and two of said 3 are ON;

the level 11 indicates that a register length is 4, and three of said 4 are ON;

the level 12 indicates that a register length is 6, and five of said 6 are ON;

the level 13 indicates that a register length is 8, and seven of said 8 are ON; and

the level 14 indicates that a register length is 12, and eleven of said 12 are ON.

20. A matrix type display unit performing multiple gradation display through frame rate control;

wherein said display unit displays 16 gradations from 0 to 15 levels, and

in the case where the gradation level 0 is assigned to a black display and the gradation level 15 is assigned to a white display,

the level 1 indicates that a register length is 12, and one of said 12 is ON;

the level 2 indicates that a register length is 8, and one of said 8 is ON;

the level 3 indicates that a register length is 6, and one of said 6 is ON;

the level 4 indicates that a register length is 4, and one of said 4 is ON;

the level 5 indicates that a register length is 3, and one of said 3 is ON;

the level 6 indicates that a register length is 8, and three of said 8 are ON;

the level 7 indicates that a register length is 12, and five of said 12 are ON;

the level 8 indicates that a register length is 2, and one of said 2 is ON;

the level 9 is a mirror construction of the level 7;

the level 10 is a mirror construction of the level 5;

the level 11 is a mirror construction of the level 4;

the level 12 is a mirror construction of the level 3;

the level 13 is a mirror construction of the level 2; and

the level 14 is a mirror construction of the level 1;

wherein said display unit comprising;

a gradation data shift circuit having multiple gradation registers which express at least one gradation of the gradation levels 1 to 8 and shifting said gradation registers; and

a gradation selection circuit formed in each segment signal line for selecting gradation data corresponding to image data based on the image data and the output data of said gradation data shift circuit;

wherein at least one of the gradation registers formed by data mirror-reversal in said gradation data shift circuit is omitted, and regarding the data of said omitted gradation registers, the data of the gradation data shift circuit is demodulated by reversing in said gradation selection circuit.

21. A display unit comprising:

a first oscillation means for generating a first frequency;

a second oscillation means for generating a second frequency;

a frequency selection means which is adapted to select the first and second frequencies generated by said first and second oscillation means, respectively;

a frequency division means for dividing the output frequencies of said frequency selection means; and

a display panel for displaying images using the output of said frequency division means are provided,

wherein when said first frequency is 100, said second frequency is in a range from 70 to 130.

22. A driving method for a display unit selecting simultaneously multiple common signal lines, said method comprising:

shifting gradation data retained in registers by one frame or one field signal and one horizontal scanning signal;

selecting gradation data corresponding to image data from said gradation data and said image data through frame rate control;

reversing a code of an orthogonal function by a selection signal which selects normally white or normally black and a polarity shifting signal for AC driving; and

selecting a voltage to be applied to segment electrodes based on said orthogonal function and said selected gradation data.