Passive redundant digital data receiver with dual comparator edge detection

• US 20040066860A1
• Filed: 10/08/2002
• Published: 04/08/2004
• Est. Priority Date: 10/08/2002
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Rannow, Randy K., Quint, David W., Bois, Karl Joseph
• Granted Patent: US 7,136,429 B2
• Time in Patent Office: Days
• US Class Current: 375/316
• CPC Class Codes: H04L 25/069 by detecting edges or zero crossings

Abstract

A passive coupling structure constructed using printed circuit board traces is used to separate the low and high frequency components of an incoming digital signal. The low and high frequency components of the signal are sent to separate receivers on an integrated circuit. The low frequency receiver may be a conventional level based receiver. The high frequency receiver is a Schmitt-trigger with hysteresis around a DC level or two comparators with separate reference voltages. The outputs of these receivers are combined to produce a receiver output that has increased reliability and noise immunity.

Claims

1. A digital signal receiver, comprising:

a passive coupling structure having a signal input, a low frequency component output, and a high frequency component output;

a level based receiver having a first input connected to said low frequency component output and a first output;

a first comparator having a first comparator output and also having a first first comparator input connected said high frequency component output and a second first comparator input connected to a first reference voltage;

a second comparator having a second comparator output and also having a first second comparator input connected to said high frequency component output and a second second comparator input connected to a second reference voltage and wherein said high frequency component output is biased to a DC voltage level that is between said first and said second reference voltage; and

,

a state machine, receiving said first and second comparator outputs and said first output, that changes a receiver output when said first output and at least one of said first and second comparator outputs transition in at least one direction.

2. The digital signal receiver of claim 1 wherein said passive coupling structure comprises a first and a second printed circuit board lines that are parallel for at least a portion of their lengths and a first end of said first line is said signal input and a second end of said first line is said low frequency component output and a first end of said second line is said high frequency component output.

3. The digital signal receiver of claim 1 wherein said state machine waits for a transition on any of said first, first comparator, and second comparator outputs and then waits a predetermined amount of time for another transition on any of said first, first comparator, and second comparator outputs to determine if said receiver output should be changed.

4. The digital signal receiver of claim 2 wherein said state machine waits for a first transition on any of said first, first comparator, and second comparator outputs and then waits a predetermined amount of time for at least a second transition on any of said first, first comparator, and second comparator outputs to determine if said receiver output should be changed.

5. The digital signal receiver of claim 1 wherein said passive coupling structure comprises a first and a second microstrip lines that are parallel for at least a portion of their lengths and a first end of said first line is said signal input and a second end of said first line is said low frequency component output and a first end of said second line is said high frequency component output.

6. The digital signal receiver of claim 4 wherein said state machine only changes said receiver output when said first transition and said second transition are consistent with a non-noise event.

7. The digital signal receiver of claim 4 wherein said state machine changes said receiver output when said first transition indicates a rising edge on said signal input and another transition also indicates a rising edge on said signal input.

8. The digital signal receiver of claim 4 wherein said state machine changes said receiver output when said first transition indicates a falling edge on said signal input and another transition also indicates a falling edge on said signal input.

9. The digital signal receiver of claim 7 wherein said first transition is indicated by a state change on said first output and said another transition is indicated by a state change on said first comparator output.

10. The digital signal receiver of claim 8 wherein said first transition is indicated by a state change on said first output and said another transition is indicated by a state change on said second comparator output.

11. The digital signal receiver of claim 7 wherein said first transition is indicated by a state change on said first comparator output and said another transition is indicated by a state change on said first output.

12. The digital signal receiver of claim 8 wherein said first transition is indicated by a state change on said second comparator output and said another transition is indicated by a state change on said first output.

13. A redundant digital receiver, comprising:

a level based receiver coupled to the low frequency output of a passive coupling structure comprised of two parallel circuit lines;

a dual comparator receiver having high and low trip points that is coupled to the high frequency output of said passive coupling structure;

at least one resistor that sets a DC bias on said high frequency output wherein said DC bias is between said high and low trip points of said dual comparator receiver; and

,

a state machine block that receives a level based output from said level based receiver and two edge based outputs from said dual comparator receiver and combines those outputs to change the state of a receiver output only when both said level based and said edge based outputs indicate that a state change on an input signal to said passive coupling structure has occurred.

14. The redundant receiver of claim 13 wherein said state machine block waits a predetermined period of time between a first transition on any of said level based output and said two edge based outputs and at least a second transition on any of said level based output and said two edge based outputs to determine if said first transition and said second transition are consistent with a non-noise event on said input signal.

15. The redundant receiver of claim 14 wherein said passive coupling structure comprises a first end of a first of said parallel circuit lines receives said input signal and a second end of said first of said parallel circuit lines is said low frequency output and a first end of a second of said parallel circuit lines is said high frequency output and a second end of said second of said parallel circuit lines is an open circuit.

16. A method of receiving digital signals, comprising:

splitting an input signal into a high frequency component and a low frequency component;

detecting a state of said low frequency component using a level based receiver to produce a level based output;

detecting an occurrence of a first edge in a first direction on said high frequency component using a first comparator to produce a first edge based output;

combining said level based and said edge based output to set the state of a receiver output when both said level based and said edge based output indicate that a state change on said input signal has occurred.

17. The method of claim 16 further comprising:

detecting an occurrence of a second edge in a second direction on said high frequency component using a second comparator to produce a second edge based output.

18. The method of claim 16 wherein said splitting is done by a passive coupling structure comprised of two parallel circuit lines.

19. The method of claim 16 wherein said receiver output is changed when said level based output indicates a change to a first logic level and said first edge based output indicates said first edge in said first direction that is towards said first logic level.

20. The method of claim 17 wherein said receiver output is changed to a first output level when said level based output indicates a change to a first logic level and said first edge based output indicates said edge in said first direction that is towards said first logic level and said receiver output is changed to a second output level when said level based output indicates a change to a second logic level and said second edge based output indicates said second edge in said second direction that is towards said second logic level.