Sputtered insulating layer for wordline stacks

• US 20040067629A1
• Filed: 08/14/2003
• Published: 04/08/2004
• Est. Priority Date: 08/31/2000
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Beaman, Kevin L.
• Granted Patent: US 6,815,372 B2
• Time in Patent Office: Days
• US Class Current: 438/586
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

Insulating material is deposited onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of:

A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and

B. Depositing by sputtering the insulating material onto the open surface of the gate dielectric separating the two wordline stacks.

Claims

1. A method of depositing an insulating material onto a gate dielectric surface separating two wordline stacks, the method comprising the steps of:

A. Forming at least two adjacent wordline stacks over a common gate dielectric the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and

B. Depositing by sputtering the insulating material onto the open surface of the gate dielectric separating the two wordline stacks.

2. The method of claim 1 in which the wordline stacks have a height h and the open surface on the gate dielectric between the stacks has a width w, the height h and width w defining an aspect ratio of w/h of at least about 2.

3. The method of claim 2 in which the insulating material is at least one of silicon dioxide, silicon nitride, boron nitride, tungsten nitride, aluminum oxide and sapphire.

4. The method claim 3 in which the insulating material is deposited at a thickness of at least about 150 angstroms.

5. The method of claim 4 in which the insulating material is deposited by collimated sputtering.

17. An integrated circuit comprising at least two wordline stacks supported on a common gate dielectric which were prepared by the method of claim 1.

18. A dynamic random access memory device comprising at least two wordline stacks supported on a common gate dielectric which were prepared by the method of claim 1.

6. A method of depositing an insulating material onto a gate dielectric surface separating two wordline stacks, each wordline stack having a top surface, the insulating material deposited as a layer onto the dielectric surface at a thickness that is substantially the same as the thickness of the insulating layer that is deposited as a layer onto the top of the stacks, the method comprising the steps of:

A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and

B. Depositing by sputtering the insulating material as a layer onto the top of the two stacks and the open surface of the gate dielectric separating the two wordline stacks.

7. The method of claim 6 in which the wordline stacks have a height h and the open surface on the gate dielectric between the stacks has a width w, the height h and width w defining an aspect ratio of w/h of at least about 2.

8. The method of claim 7 in which the insulating material is at least one of silicon dioxide, silicon nitride, boron nitride, tungsten nitride, aluminum oxide and sapphire.

9. The method claim 8 in which the insulating material is deposited at a thickness of at least about 150 angstroms.

10. The method of claim 9 in which the insulating material is deposited by collimated sputtering.

11. A method of depositing an insulating material onto a gate dielectric surface separating two wordline stacks, each wordline stack having a top surface and at least one side wall, the insulating material deposited as a layer onto the dielectric surface (i) at a thickness that is substantially the same as the thickness of the insulating layer that is deposited as a layer onto the top of the stacks, and (ii) without any substantial deposition of the insulating material onto the side walls of the stacks, the method comprising the steps of:

A. Forming at least two adjacent wordline stacks over a common gate dielectric, the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and

B. Depositing by sputtering the insulating layer onto the top of the two stacks and the open surface of the gate dielectric separating the two wordline stacks without any substantial deposition of the insulating material onto the side walls of the stacks.

12. The method of claim 11 in which the wordline stacks have a height h and the open surface on the gate dielectric between the stacks has a width w, the height h and width w defining an aspect ratio of w/h of at least about 2.

13. The method of claim 12 in which the insulating material is at least one of silicon dioxide, silicon nitride, boron nitride, tungsten nitride, aluminum oxide and sapphire.

14. The method claim 13 in which the insulating material is deposited at a thickness of at least about 150 angstroms.

15. The method of claim 14 in which the insulating material is deposited by collimated sputtering.

16. In a method of fabricating an integrated circuit on a wafer, the method comprising the steps of:

A. Forming at least two wordline stacks over a common gate dielectric, each wordline stack having a top surface and at least one side wall and the stacks spaced apart from one another thereby forming an open surface on the gate dielectric between the stacks; and

B. Depositing an insulating material onto the top of the two stacks and the open surface of the gate dielectric separating the two stacks;

the improvement comprising depositing the insulating material by sputtering.