Reduction of seed layer roughness for use in forming SiGe gate electrode

• US 20040067631A1
• Filed: 10/03/2002
• Published: 04/08/2004
• Est. Priority Date: 10/03/2002
• Status: Abandoned Application

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Niimi, Hiroaki, Bu, Haowen, Khamankar, Rajesh, Butler, Stephanie Watts
• Application Number:
  US10/263,521
• Publication Number:
  US 20040067631A1
• Time in Patent Office: Days
• US Class Current: 438/592
• CPC Class Codes: H01L 21/2807 the final conductor layer next to the insulator being Si or Ge or C and their alloys except Si
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/32055 Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers

Abstract

Seed layer roughness can be reduced in conjunction with formation of a SiGe gate electrode. Surface characteristics of a gate dielectric can be modified, such by use of a nitrogen containing gas, prior to deposition of the seed layer on to the dielectric. The modifications in surface characteristics enable a thin seed layer to be formed overlying the gate dielectric with a reduced roughness relative to many conventional approaches.

Claims

1. A fabrication method to reduce roughness of a seed layer for use in a gate electrode, comprising:

pre-treating a surface of a gate dielectric layer associated with the gate electrode; and

forming a seed layer overlying the pre-treated surface of the gate dielectric layer.

2. The method of claim 1, further comprising providing a substrate and forming the gate dielectric layer overlying an exposed surface of the substrate.

3. The method of claim 2, the gate dielectric layer comprising at least one of silicon dioxide (SiO₂) and a material having a dielectric coefficient that exceeds SiO₂.

4. The method of claim 2, further comprising forming a silicon germanium (SiGe) layer overlying the seed layer.

5. The method of claim 4 implemented as part of a transistor fabrication process, the transistor fabrication process, further comprising:

forming a gate dielectric stack that includes at least the gate dielectric layer, the seed layer, and the SiGe layer; and

forming source and drain regions in the substrate generally aligned relative to edges of the gate dielectric stack.

6. The method of claim 1, the pre-treating further comprising annealing the surface of the gate dielectric layer in a nitrogen containing gas.

7. The method of claim 6, the annealing further comprising annealing with one of ammonia (NH₃) and deuterated ammonia (ND₃) at a temperature greater than about 500°

C.

8. The method of claim 1, further comprising employing nitridation to pre-treat the gate dielectric layer.

9. The method of claim 8, the nitridation further comprising plasma nitridation.

10. The method of claim 1, the formation of the seed layer further comprising forming a Si seed layer overlying the pre-treated gate dielectric so as to have a thickness less than or equal to about 50 angstroms.

11. The method of claim 10, the formation of the Si seed layer further comprising depositing SiH₄ overlying the pre-treated gate dielectric at a flow rate of greater than about 50 stand cubic centimeters per minute.

12. The method of claim 10, the Si seed layer having a thickness that is less than or equal to about 30 angstroms.

13. The method of claim 1, the pre-treating of the gate dielectric layer and the formation of the seed layer being performed consecutively as an integrated process in at least one of a common process chamber and cluster.

14. A method for fabricating layers for use in formation of a silicon germanium (SiGe) gate electrode, comprising:

providing a substrate having a first surface;

forming a gate dielectric layer overlying the first surface of the substrate;

treating the gate dielectric layer with a gaseous medium to modify a surface characteristic of the gate dielectric;

forming a seed layer overlying the treated gate dielectric, whereby the treating mitigates roughness of the seed layer; and

forming a SiGe layer overlying the seed layer, such that germanium (Ge) interdiffuses into the seed layer.

15. The method of claim 14, the gate dielectric layer comprising at least one of silicon dioxide (SiO₂) and a material having a dielectric coefficient that exceeds SiO₂.

16. The method of claim 14, the treating further comprising annealing the surface of the gate dielectric layer in process chamber in a nitrogen-containing gaseous medium.

17. The method of claim 16, the annealing further comprising annealing with one of NH₃ and ND₃ at a temperature greater than about 550°

C.

18. The method of claim 14, further comprising employing nitridation to treat the gate dielectric layer.

19. The method of claim 14, the formation of the seed layer further comprising forming the seed layer by depositing silicon overlying the pre-treated gate dielectric so as to form the seed layer having a thickness less than or equal to about 50 angstroms.

20. The method of claim 19, the formation of the Si seed layer further comprising depositing SiH₄ overlying the pre-treated gate dielectric at a flow rate of greater than about 50 SCCM and at a temperature in a range from about 450°

C. to about 650°

C.

21. The method of claim 19, the Si seed layer having a thickness that is less than or equal to about 30 angstroms.

22. The method of claim 14, the treating of the gate dielectric layer and the formation of the seed layer being performed consecutively as an integrated process in at least one of a common process chamber and a cluster.

23. The method of claim 22, further comprising evacuating the process chamber after the treating of the gate dielectric layer.

24. The method of claim 14 implemented as part of a transistor fabrication process, the transistor fabrication process, further comprising:

forming a gate dielectric stack that includes the gate dielectric layer, the seed layer, and the SiGe layer; and

forming source and drain regions in the substrate generally aligned relative to respective edges of the gate dielectric stack.

25. The method of claim 24, further comprising, prior to forming the gate dielectric stack, forming a cap layer overlying the SiGe layer, such that the formation of the gate dielectric stack also includes the cap layer.

26. A processing system for use in forming at least part of a gate electrode stack on a silicon substrate, comprising:

means for pre-treating an exposed surface of a gate dielectric layer overlying the substrate so as to modify a surface characteristic of the gate dielectric layer; and

means for forming a seed layer overlying the pre-treated surface of the gate dielectric layer, whereby roughness of the seed layer is mitigated based on pre-treatment of the gate dielectric layer provided by the means for pre-treating.