Apparatus, method and system for accelerated graphics port bus bridges

• US 20040068602A1
• Filed: 10/06/2003
• Published: 04/08/2004
• Est. Priority Date: 09/24/1998
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Olarig, Sompong Paul, Horan, Ronald Timothy, Rajagopalan, Usha
• Application Number:
  US10/679,734
• Publication Number:
  US 20040068602A1
• Time in Patent Office: Days
• US Class Current: 710/306
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices

Abstract

A computer system having at least one central processing unit, system memory, and a core logic capable of accepting an AGP bus is provided with an AGP to AGP bridge connected to the standard AGP bus. The AGP to AGP bridge can accommodate two or more AGP-compatible devices that can be accessed through the standard AGP bus via the AGP to AGP bridge. A PCI to memory bridge is also provided within the AGP to AGP bridge so that PCI devices may be connected to the AGP to AGP bridge. The AGP to AGP bridge is fitted with an overall flow control logic that controls the transfer of data to or from the various AGP devices and the standard AGP bus that is connected to the core logic of the computer system. The AGP to AGP Bridge can utilize a standard 32-bit AGP bus as well as (two) dual 32-bit buses to enhance bandwidth. In an alternate embodiment of the invention, the dual 32-bit buses can be combined to form a single 64-bit bus to increase the available bandwidth. Alternate embodiments of the AGP to AGP Bridge can accommodate the single 64-bit AGP bus for increased performance. Another alternate embodiment can accommodate peer-to-peer transfer of data between AGP busses on the bridge.

Claims

1. A computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, system random access memory connected to said core logic, and a first AGP bus connected to said core logic, said apparatus further comprising:

an AGP to AGP bridge, said AGP to AGP bridge constructed and arranged to connect at least two AGP-compatible devices to said computer system via said first AGP bus.

2. A computer system as in claim 1, wherein said first AGP bus is a 32-bit bus.

3. A computer system as in claim 2, said AGP to AGP bridge further comprising:

a first interface target and arbiter connected to said first AGP bus;

a first read data return queue connected to said first interface target and arbiter;

a first read and write request queue connected to said first interface target and arbiter;

a first write data queue connected to said first interface target and arbiter;

a second interface target and arbiter connected to a second AGP bus;

a second read data return queue connected to said second interface target and arbiter, said second read data return queue further connected to said first read data return queue;

a second read and write request queue connected to said second interface target and arbiter, said second read and write request queue further connected to said first read and write request queue;

a second write data queue connected to said second interface target and arbiter, said second write data queue further connected to said first write data queue;

a third interface target and arbiter connected to a third AGP bus;

a third read data return queue connected to said third interface target and arbiter, said third read data return queue further connected to said first read data return queue;

a third read and write request queue connected to said third interface target and arbiter, said third read and write request queue further connected to said first read and write request queue;

a third write data queue connected to said third interface target and arbiter, said third write data queue further connected to further connected to said first write data queue; and

a flow control logic, said flow control logic connected to said first read data return queue, said first read and write request queue, said first write data queue, said first interface target and arbiter, said second read data return queue, said second read and write request queue, said second write data queue, said second interface target and arbiter, said third read data return queue, said third read and write request queue, said third write data queue, and said third interface target and arbiter;

wherein said flow control logic regulates the transfer of requests, replies, and data between said first AGP bus, said second AGP bus and said third AGP bus.

4. A computer system as in claim 3, wherein said AGP to AGP bridge has a PCI interface.

5. A computer system as in claim 4, wherein said PCI interface comprises:

a first PCI master/target interface connected to said first AGP bus;

a first PCI target state machine connected to said first PCI master/target interface;

a first PCI master state machine connected to said first PCI master/target interface;

a second PCI master/target arbiter connected to said second AGP bus;

a second PCI target state machine connected to said second PCI master/target arbiter and to said first PCI target state machine;

a second PCI master state machine connected to said second PCI master/target arbiter and to said first PCI master state machine;

a third PCI master/target arbiter connected to said third AGP bus;

a third PCI target state machine connected to said third PCI master/target arbiter and to said first PCI target state machine; and

a third PCI master state machine connected to said third PCI master/target arbiter and to said first PCI master state machine;

wherein said PCI interface handles request, reply, and data transfers between said first AGP bus, said second AGP bus and said third AGP bus within the PCI protocol.

6. A computer system as in claim 1, wherein said first AGP bus is a 64-bit bus acting as a first 32-bit AGP bus and a second 32-bit AGP bus, said first and said second 32-bit AGP buses capable of operating concurrently.

7. A computer system as in claim 1, wherein said first AGP bus is a 64-bit bus and said AGP to AGP bridge is an ASIC that interfaces directly with said core logic, said first AGP bus behaves as a superset of the standard 32-bit AGP bus.

8. A computer system as in claim 7, wherein said AGP to AGP bridge further comprises an REQ64#, an ACK64#, a C/BE[7:

4]#, an AD[63;

32], and an ST[3;

2].

13. A computer system as in claim 1, said computer system further comprising a geometry processor connected to said AGP to AGP bridge.

14. A computer system as in claim 1, said computer system further comprising a rendering processor connected to said AGP to AGP bridge.

15. A computer system as in claim 1, said computer system further comprising a geometry processor and a rendering processor, each of said processors connected to said AGP to AGP bridge.

16. A computer system as in claim 15, wherein said geometry processor and said rendering processor can communicate without using said core logic.

17. A computer system as in claim 15, wherein said geometry process and said rendering processor reside on a printed circuit board.

18. A computer system as in claim 13, wherein said geometry processor resides on a geometry processor board.

19. A computer system as in claim 14, wherein said rendering processor resides on a rendering processor board.

9. A computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, system random access memory connected to said core logic, and a first AGP bus connected to said core logic, said apparatus further comprising:

a first AGP bus connected to said core logic, said first AGP bus consisting of a 64-bit bus that is configured as two 32-bit buses, each of said 32-bit buses acts as a standard AGP bus to said core logic, each of said 32-bit bus can operate concurrently with the other of said 32-bit bus.

10. A computer system as in claim 9, wherein said AGP to AGP bridge has a PCI interface.

11. A computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, and system random access memory connected to said core logic, said apparatus further comprising:

a first AGP bus connected to said core logic, said first AGP bus being a 64-bit bus.

12. A computer system as in claim 11, wherein an AGP to AGP bridge is connected to said first AGP bus, said AGP to AGP bridge being an ASIC that interfaces directly with said core logic.

20. A method of transferring data within a computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, system random access memory connected to said core logic, and a first AGP bus connected to said core logic, said computer system further having an AGP to AGP bridge, said AGP to AGP bridge constructed and arranged to connect at least two AGP-compatible devices to said computer system via said first AGP bus, said AGP to AGP bridge further having a first interface target and arbiter connected to said first AGP bus, a first read data return queue connected to said first interface target and arbiter, a first read and write request queue connected to said first interface target and arbiter, a first write data queue connected to said first interface target and arbiter, a second interface target and arbiter connected to a second AGP bus, a second read data return queue connected to said second interface target and arbiter, said second read data return queue further connected to said first read data return queue, a second read and write request queue connected to said second interface target and arbiter, said second read and write request queue further connected to said first read and write request queue, a second write data queue connected to said second interface target and arbiter, said second write data queue further connected to said first write data queue, a third interface target and arbiter connected to a third AGP bus, a third read data return queue connected to said third interface target and arbiter, said third read data return queue further connected to said first read data return queue, a third read and write request queue connected to said third interface target and arbiter, said third read and write request queue further connected to said first read and write request queue, a third write data queue connected to said third interface target and arbiter, said third write data queue further connected to said first write data queue, and a flow control logic, said flow control logic connected to said first read data return queue, said first read and write request queue, said first write data queue, said first interface target and arbiter, said second read data return queue, said second read and write request queue, said second write data queue, said second interface target and arbiter, said third read data return queue, said third read and write request queue, said third write data queue, and said third interface target and arbiter, said method comprising the steps of:

(a) transferring data between said first AGP bus and said second AGP bus.

23. The method of claim 20, wherein said step (a) further comprises the steps of:

(a1) if the request is on said second AGP bus, then adding said request to said second AGP read and write request queue; and

(a2) reorder request according to a set of ordering rules.

24. The method of claim 20, wherein said step (a) further comprises the steps of:

(a1) issuing a signal from said overall flow control logic to start a transaction;

(a2) arbitrating and starting a read reply transaction;

(a3) getting data from said second AGP read data return queue; and

(a4) inserting wait states upon instructions from said flow control logic.

27. The method of claim 20, wherein said step (a) further comprises the steps of:

(a1) if a request is in said first AGP read and write request queue and if further requests can be queued to said first AGP bus target, then arbitrating and queuing said requests; and

(a2) changing the status of said request in said first AGP read and write request queue.

30. The method of claim 20, wherein said step (a) further comprising the steps of:

(a1) checking to determine if a reply is in said first AGP bus;

(a2) if the result of said step (a1) is positive, then checking to see if said reply is a write;

(a3) if the result of said step (a2) is positive, then supplying data from said first AGP write data queue, and retiring from said first AGP read and write request queue and from said first AGP read data return queue and repeating said step (a1);

(a4) if the result of said step (a2) is negative, then checking to see if said reply is a read;

(a5) if the result of said step (a4) is negative, then checking to see if said reply is a fence;

(a6) if the result of said step (a5) is positive, then completing the access and triggering said flow control logic and repeating said step (a1);

(a7) if the result of said step (a4) is positive, then storing data in said first AGP read data return queue, moving corresponding read request into said first AGP read data return queue, triggering said flow control logic to start moving said data towards either to said second AGP bus or to said third AGP bus;

(a8) inserting at least one wait state at a subsequent block if said first AGP read data return queue is full until complete access has been completed on said first AGP bus;

(a9) checking to determine if an RBF# has been asserted;

(a10) if the result of said step (a9) is negative, then performing said step (a5); and

(a11) if the result of said step (a9) is positive, then utilizing a spillover buffer space and inserting wait state on a subsequent boundary, and performing said step (a1).

33. The method of claim 20, wherein said step (a) further comprises the steps of

(a1) checking to determine if a request is in said second AGP read and write request queue;

(a2) if the result of said step (a1) is negative, then handling said request as being in said third AGP read and write request queue;

(a3) if the result of said step (a1) is positive, then checking to determine if said request is a write;

(a4) if the result of said step (a3) is positive, then checking to determine if said write request is complete in said second AGP bus;

(a5) if said result of said step (a4) is positive, then handling said request as being in said third AGP read and write request queue;

(a6) if the result of said step (a4) is negative, then checking to determine if there is space in said second AGP write data queue for an entire access;

(a7) if the result of said step (a6) is negative, then handling said request as being in said third AGP read and write request queue;

(a8) if said result of said step (a6) is positive, then running a write cycle on said second AGP bus and storing write data in said second AGP write data queue, and marking said request as completed on said second AGP bus;

(a9) after said step (a8), or if said result of said step (a2) is negative, then checking to determine if space is available in said first AGP read and write request queue;

(a10) if said result of said step (a9) is negative, then executing said step (a1);

(a11) if said result of said step (a9) is positive, then checking to determine if said request is a write;

(a12) if the result of said step (a11) is negative, then transferring said request to said first AGP read and write request queue and re-ordering said first AGP read and write request queue according to a set of ordering rules and then handling said request as being in said third AGP read and write request queue;

(a13) if said result of said step (a11) is positive, then checking to determine if there is space available in said first AGP write data queue;

(a14) if the result of said step (a13) is negative, then executing said step (a1); and

(a15) if said result of said step (a13) is positive, then transferring data and transferring said request to said first AGP write data queue, reording said first AGP write data queue according to a set of ordering rules, and then handling said request as being in said third AGP read and write request queue.

35. The method of claim 20, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a request is in said third AGP read and write request queue;

(a2) if the result of said step (a1) is negative, then handling said request as being in said second AGP read and write request queue;

(a3) if the result of said step (a1) is positive, then checking to determine if said request is a write;

(a4) if the result of said step (a3) is positive, then checking to determine if said write request is complete in said second AGP bus;

(a5) if the result of said step (a4) is negative, then checking to determine if there is space in said third AGP write data queue for an entire access;

(a6) if the result of said step (a5) is negative, then executing said step (a1);

(a7) if said result of said step (a5) is positive, then running a write cycle on said third AGP bus and storing write data in said third AGP write data queue, and marking said request as completed on said third AGP bus;

(a8) after said step (a7), or if said result of said step (a3) is negative, or if said result of said step (a4) is positive, then checking to determine if space is available in said first AGP read and write request queue;

(a9) if said result of said step (a8) is negative, then executing said step (a1);

(a10) if said result of said step (a8) is positive, then checking to determine if said request is a write;

(a11) if the result of said step (a10) is negative, then transferring said request to said first AGP read and write request queue and re-ordering said first AGP read and write request queue according to a set of ordering rules and then handling said request as being in said second AGP read and write request queue;

(a12) if said result of said step (a10) is positive, then checking to determine if there is space available in said first AGP write data queue;

(a13) if the result of said step (a12) is negative, then executing said step (a1); and

(a14) if said result of said step (a12) is positive, then transferring data and transferring said request to said first AGP write data queue, reording said first AGP write data queue according to a set of ordering rules, and then handling said request as being in said second AGP read and write request queue.

37. The method according to claim 20, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a next read request on said first AGP read and write request queue is small enough to fit within an internal buffer space within said AGP to AGP bridge;

(a2) if the result of said step (a1) is positive, then executing said step (a1);

(a3) if said result of said step (a1) is negative, then checking to determine if said next read request is from said second AGP bus;

(a4) if said result of said step (a3) is positive, then checking to determine if an RBF# has been asserted on said second AGP bus;

(a5) if the result of said step (a4) is negative, then executing said step (a1);

(a6) if the result of said step (a4) is positive, then asserting an RBF# on said first AGP bus;

(a7) checking to determine if said RBF# on said second AGP bus is deasserted;

(a8) if the result of step (a7) is negative, then executing step (a7);

(a9) if said result of step (a7) is positive, then deasserting said RBF# of said first AGP bus and then executing said step (a1);

(a10) if said result of said step (a3) is negative, then checking to determine if said next read request is from said third AGP bus;

(a11) if the result of said step (a10) is positive, then checking to determine if an RBF# on said third AGP bus has been asserted;

(a12) if the result of said step (a11) is negative then executing said step (a1);

(a13) if said result of said step (a11) is positive, then asserting said RBF# of said first AGP bus;

(a14) checking to determine if said RBF# of said third AGP bus is deasserted;

(a15) if the result of said step (a14) is negative, then executing said step (a14); and

(a16) if said result of said step (a14) is positive, then deasserting said RBF# of said first AGP bus and executing said step (a1).

39. The method of claim 20, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a reply in said first AGP read data return queue;

(a2) if the result of said step (a1) is positive, then checking to determine if said replay is for said second AGP bus;

(a3) if the result of said step (a2) is positive, then checking to determine if sufficient space exists within said second AGP read data queue;

(a4) if the result of said step (a3) is positive, then transferring data to said second read data return queue, triggering said second AGP bus interface to start transacting on said second AGP bus, completing said transfer of said request, otherwise waiting for said second AGP read data return queue to empty in order to complete said transfer, and then executing said step (a1);

(a5) if said result of said step (a2) is negative, then checking to determine if said reply is for said third AGP bus;

(a6) if the result of said step (a5) is positive, then checking to determine if space is available to fulfill said request in said third read data return queue; and

(a7) if the result of said step (a6) is positive, then transferring data to said third read data return queue, triggering said third AGP bus interface to start transacting on said third AGP bus, completing said transfer of said request, and then executing said step (a1).

21. A method of transferring data within a computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, system random access memory connected to said core logic, and a first AGP bus connected to said core logic, said computer system further having an AGP to AGP bridge, said AGP to AGP bridge constructed and arranged to connect at least two AGP-compatible devices to said computer system via said first AGP bus, said AGP to AGP bridge further having a first interface target and arbiter connected to said first AGP bus, a first read data return queue connected to said first interface target and arbiter, a first read and write request queue connected to said first interface target and arbiter, a first write data queue connected to said first interface target and arbiter, a second interface target and arbiter connected to a second AGP bus, a second read data return queue connected to said second interface target and arbiter, said second read data return queue further connected to said first read data return queue, a second read and write request queue connected to said second interface target and arbiter, said second read and write request queue further connected to said first read and write request queue, a second write data queue connected to said second interface target and arbiter, said second write data queue further connected to said first write data queue, a third interface target and arbiter connected to a third AGP bus, a third read data return queue connected to said third interface target and arbiter, said third read data return queue further connected to said first read data return queue, a third read and write request queue connected to said third interface target and arbiter, said third read and write request queue further connected to said first read and write request queue, a third write data queue connected to said third interface target and arbiter, said third write data queue further connected to said first write data queue, and a flow control logic, said flow control logic connected to said first read data return queue, said first read and write request queue, said first write data queue, said first interface target and arbiter, said second read data return queue, said second read and write request queue, said second writ data queue, said second interface target and arbiter, said third read data return queue, said third read and write request queue, said third write data queue, and said third interface target and arbiter, said method comprising the steps of:

(a) transferring data between said first AGP bus and said third AGP bus.

25. The method of claim 21, wherein said step (a) further comprises the steps of:

(a1) if the request is on said third AGP bus, then adding said request to said third AGP read and write request queue; and

(a2) reorder requests according to a set of ordering rules.

26. The method of claim 21, wherein said step (a) further comprises the steps of:

(a1) issuing a signal from said flow control logic to start a transaction;

(a2) arbitrating and starting a read reply transaction;

(a3) getting data from said third AGP read data return queue; and

(a4) inserting wait states upon instructions from said flow control logic.

28. The method of claim 21, wherein said step (a) further comprises the steps of:

(a1) if a request is in said first AGP read and write request queue and if further requests can be queued to said first AGP bus target, then arbitrating and queuing said requests; and

(a2) changing the status of said request in said first AGP read and write request queue.

31. The method of claim 21, wherein said step (a) further comprising the steps of:

(a1) checking to determine if a reply is in said first AGP bus;

(a2) if the result of said step (a1) is positive, then checking to see if said reply is a write;

(a3) if the result of said step (a2) is positive, then supplying data from said first AGP write data queue, and retiring from said first AGP read and write request queue and from said first AGP read data return queue and repeating said step (a1);

(a4) if the result of said step (a2) is negative, then checking to see if said reply is a read;

(a5) if the result of said step (a4) is negative, then checking to see if said reply is a fence;

(a6) if the result of said step (a5) is positive, then completing the access and triggering said flow control logic and repeating said step (a1);

(a7) if the result of said step (a4) is positive, then storing data in said first AGP read data return queue, moving corresponding read request into said first AGP read data return queue, triggering said flow control logic to start moving said data towards either to said second AGP bus or to said third AGP bus;

(a8) inserting at least one wait state at a subsequent block if said first AGP read data return queue is full until complete access has been completed on said first AGP bus;

(a9) checking to determine if an RBF# has been asserted;

(a10) if the result of said step (a9) is negative, then performing said step (a5); and

(a11) if the result of said step (a9) is positive, then utilizing a spillover buffer space and inserting wait state on a subsequent boundary, and performing said step (a1).

34. The method of claim 21, wherein said step (a) further comprises the steps of

(a1) checking to determine if a request is in said second AGP read and write request queue;

(a2) if the result of said step (a1) is negative, then handling said request as being in said third AGP read and write request queue;

(a3) if the result of said step (a1) is positive, then checking to determine if said request is a write;

(a4) if the result of said step (a3) is positive, then checking to determine if said write request is complete in said second AGP bus;

(a5) if said result of said step (a4) is positive, then handling said request as being in said third AGP read and write request queue;

(a6) if the result of said step (a4) is negative, then checking to determine if there is space in said second AGP write data queue for an entire access;

(a7) if the result of said step (a6) is negative, then handling said request as being in said third AGP read and write request queue;

(a8) if said result of said step (a6) is positive, then running a write cycle on said second AGP bus and storing write data in said second AGP write data queue, and marking said request as completed on said second AGP bus;

(a9) after said step (a8), or if said result of said step (a2) is negative, then checking to determine if space is available in said first AGP read and write request queue;

(a10) if said result of said step (a9) is negative, then executing said step (a1);

(a11) if said result of said step (a9) is positive, then checking to determine if said request is a write;

(a12) if the result of said step (a11) is negative, then transferring said request to said first AGP read and write request queue and re-ordering said first AGP read and write request queue according to a set of ordering rules and then handling said request as being in said third AGP read and write request queue;

(a13) if said result of said step (a11) is positive, then checking to determine if there is space available in said first AGP write data queue;

(a14) if the result of said step (a13) is negative, then executing said step (a1); and

(a15) if said result of said step (a13) is positive, then transferring data and transferring said request to said first AGP write data queue, reording said first AGP write data queue according to a set of ordering rules, and then handling said request as being in said third AGP read and write request queue.

36. The method of claim 21, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a request is in said third AGP read and write request queue;

(a2) if the result of said step (a1) is negative, then handling said request as being in said second AGP read and write request queue;

(a3) if the result of said step (a1) is positive, then checking to determine if said request is a write;

(a4) if the result of said step (a3) is positive, then checking to determine if said write request is complete in said second AGP bus;

(a5) if the result of said step (a4) is negative, then checking to determine if there is space in said third AGP write data queue for an entire access;

(a6) if the result of said step (a5) is negative, then executing said step (a1);

(a7) if said result of said step (a5) is positive, then running a write cycle on said third AGP bus and storing write data in said third AGP write data queue, and marking said request as completed on said third AGP bus;

(a8) after said step (a7), or if said result of said step (a3) is negative, or if said result of said step (a4) is positive, then checking to determine if space is available in said first AGP read and write request queue;

(a9) if said result of said step (a8) is negative, then executing said step (a1);

(a10) if said result of said step (a8) is positive, then checking to determine if said request is a write;

(a11) if the result of said step (a10) is negative, then transferring said request to said first AGP read and write request queue and re-ordering said first AGP read and write request queue according to a set of ordering rules and then handling said request as being in said second AGP read and write request queue;

(a12) if said result of said step (a10) is positive, then checking to determine if there is space available in said first AGP write data queue;

(a13) if the result of said step (a12) is negative, then executing said step (a1); and

(a14) if said result of said step (a12) is positive, then transferring data and transferring said request to said first AGP write data queue, reording said first AGP write data queue according to a set of ordering rules, and then handling said request as being in said second AGP read and write request queue.

38. The method according to claim 21, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a next read request on said first AGP read and write request queue is small enough to fit within an internal buffer space within said AGP to AGP bridge;

(a2) if the result of said step (a1) is positive, then executing said step (a1);

(a3) if said result of said step (a1) is negative, then checking to determine if said next read request is from said second AGP bus;

(a4) if said result of said step (a3) is positive, then checking to determine if an RBF# has been asserted on said second AGP bus;

(a5) if the result of said step (a4) is negative, then executing said step (a1);

(a6) if the result of said step (a4) is positive, then asserting an RBF# on said first AGP bus;

(a7) checking to determine if said RBF# on said second AGP bus is deasserted;

(a8) if the result of step (a7) is negative, then executing step (a7);

(a9) if said result of step (a7) is positive, then deasserting said RBF# of said first AGP bus and then executing said step (a1);

(a10) if said result of said step (a3) is negative, then checking to determine if said next read request is from said third AGP bus;

(a11) if the result of said step (a10) is positive, then checking to determine if an RBF# on said third AGP bus has been asserted;

(a12) if the result of said step (a11) is negative then executing said step (a1);

(a13) if said result of said step (a11) is positive, then asserting said RBF# of said first AGP bus;

(a14) checking to determine if said RBF# of said third AGP bus is deasserted;

(a15) if the result of said step (a14) is negative, then executing said step (a14); and

(a16) if said result of said step (a14) is positive, then deasserting said RBF# of said first AGP bus and executing said step (a1).

40. The method of claim 21, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a reply in said first AGP read data return queue;

(a2) if the result of said step (a1) is positive, then checking to determine if said replay is for said second AGP bus;

(a3) if the result of said step (a2) is positive, then checking to determine if sufficient space exists within said second AGP read data queue;

(a4) if the result of said step (a3) is positive, then transferring data to said second read data return queue, triggering said second AGP bus interface to start transacting on said second AGP bus, completing said transfer of said request, otherwise waiting for said second AGP read data return queue to empty in order to complete said transfer, and then executing said step (a1);

(a5) if said result of said step (a2) is negative, then checking to determine if said reply is for said third AGP bus;

(a6) if the result of said step (a5) is positive, then checking to determine if space is available to fulfill said request in said third read data return queue; and

(a7) if the result of said step (a6) is positive, then transferring data to said third read data return queue, triggering said third AGP bus interface to start transacting on said third AGP bus, completing said transfer of said request, and then executing said step (a1).

22. A method of transferring data within a computer system, said computer system having a central processing unit, a core logic connected to said central processing unit, system random access memory connected to said core logic, and a first AGP bus connected to said core logic, said computer system further having an AGP to AGP bridge, said AGP to AGP bridge constructed and arranged to connect at least two AGP-compatible devices to said computer system via said first AGP bus, said AGP to AGP bridge further having a first interface target and arbiter connected to said first AGP bus, a first read data return queue connected to said first interface target and arbiter, a first read and write request queue connected to said first interface target and arbiter, a first write data queue connected to said first interface target and arbiter, a second interface target and arbiter connected to a second AGP bus, a second read data return queue connected to said second interface target and arbiter, said second read data return queue further connected to said first read data return queue, a second read and write request queue connected to said second interface target and arbiter, said second read and write request queue further connected to said first read and write request queue, a second write data queue connected to said second interface target and arbiter, said second write data queue further connected to said first write data queue, a third interface target and arbiter connected to a third AGP bus, a third read data return queue connected to said third interface target and arbiter, said third read data return queue further connected to said first read data return queue, a third read and write request queue connected to said third interface target and arbiter, said third read and write request queue further connected to said first read and write request queue, a third write data queue connected to said third interface target and arbiter, said third write data queue further connected to said first write data queue, and a flow control logic, said flow control logic connected to said first read data return queue, said first read and write request queue, said first write data queue, said first interface target and arbiter, said second read data return queue, said second read and write request queue, said second write data queue, said second interface target and arbiter, said third read data return queue, said third read and write request queue, said third write data queue, and said third interface target and arbiter, said method comprising the steps of:

(a) transferring data between said second AGP bus and said third AGP bus.

29. The method of claim 22, wherein said step (a) further comprises the steps of:

(a1) if the request is in said first AGP read and write request queue and if further requests can be queued to said first AGP bus target, then arbitrating and queuing said requests; and

(a2) changing the status of said request in said first AGP read and write request queue.

32. The method of claim 22, wherein said step (a) further comprising the steps of:

(a1) checking to determine if a reply is in said first AGP bus;

(a2) if the result of said step (a1) is positive, then checking to see if said reply is a write;

(a3) if the result of said step (a2) is positive, then supplying data from said first AGP write data queue, and retiring from said first AGP read and write request queue and from said first AGP read data return queue and repeating said step (a1);

(a4) if the result of said step (a2) is negative, then checking to see if said reply is a read;

(a5) if the result of said step (a4) is negative, then checking to see if said reply is a fence;

(a6) if the result of said step (a5) is positive, then completing the access and triggering said flow control logic and repeating said step (a1);

(a7) if the result of said step (a4) is positive, then storing data in said first AGP read data return queue, moving corresponding read request into said first AGP read data return queue, triggering said flow control logic to start moving said data towards either to said second AGP bus or to said third AGP bus;

(a8) inserting at least one wait state at a subsequent block if said first AGP read data return queue is full until complete access has been completed on said first AGP bus;

(a9) checking to determine if an RBF# has been asserted;

(a10) if the result of said step (a9) is negative, then performing said step (a5); and

(a11) if the result of said step (a9) is positive, then utilizing a spillover buffer space and inserting wait state on a subsequent boundary, and performing said step (a1).

41. The method of claim 22, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a request in said second AGP read and write request queue;

(a2) if the result of said step (a1) is negative, then executing said step (a1);

(a3) if said result of said step (a1) is positive, then checking to determine if said request is a peer-to-peer request;

(a4) if the result of said step (a3) is negative, then transferring said request to said first AGP read and write request queue; and

(a5) if said result of said step (a3) is positive, then transferring said request to said third APG read and write request queue.

42. The method of claim 22, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a request in said third AGP read and write request queue;

(a2) if the result of said step (a1) is negative, then executing said step (a1);

(a3) if said result of said step (a1) is positive, then checking to determine if said request is a peer-to-peer request;

(a4) if the result of said step (a3) is negative, then transferring said request to said first AGP read and write request queue; and

(a5) if said result of said step (a3) is positive, then transferring said request to said second APG read and write request queue.

43. The method of claim 22, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a reply is in said second AGP read data return queue;

(a2) if the result of said step (a1) is negative, then executing said step (a1); and

(a3) if said result of said step (a1) is positive, then transferring data to said third AGP read data return queue.

44. The method of claim 22, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a reply is in said third AGP read data return queue;

(a2) if the result of said step (a1) is negative, then executing said step (a1); and

(a3) if said result of said step (a1) is positive, then transferring data to said second AGP read data return queue.

45. The method of claim 22, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a request is in said second AGP write data queue;

(a2) if the result of said step (a1) is negative, then executing said step (a1);

(a3) if said result of said step (a1) is positive, then transferring data to said third AGP write data queue.

46. The method of claim 22, wherein said step (a) further comprises the steps of:

(a1) checking to determine if a request is in said third AGP write data queue;

(a2) if the result of said step (a1) is negative, then executing said step (a1);

(a3) if said result of said step (a1) is positive, then transferring data to said second AGP write data queue.