System and method for managing the operating frequency of processors or blades

• US 20040068673A1
• Filed: 08/12/2002
• Published: 04/08/2004
• Est. Priority Date: 08/12/2002
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Espinoza-Ibarra, Ricardo, Barr, Andrew H.
• Granted Patent: US 7,124,315 B2
• Time in Patent Office: Days
• US Class Current: 713/501
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a system and method for managing the operating frequency of processors in a blade-based computer system, a circuit receives a signal with instructions relating to the desired operating frequency of the processors or blades. The circuit then generates a control signal based upon the specific frequency designated by the user. A frequency synthesizer then processes an input frequency signal and the control signal and outputs an output frequency to be

Claims

1. A method for managing the operating frequency of processors in a blade-based computer system, said method comprising the steps of:

using a circuit to control a frequency synthesizer in said blade-based computer system;

generating, by said circuit, a control signal based upon inputs to the circuit by a user of said blade-based computer system;

processing, by said frequency synthesizer, an input frequency signal and said control signal from said circuit; and

outputting, by said frequency synthesizer, an output frequency to be used by said individual processors in said blade-based computer system.

2. The method according to claim 1, wherein said method adjusts the frequency level of individual processors to modulate the frequency within at least one blade at the processor level.

3. The method according to claim 1, wherein said method adjusts the frequency level of at least one processor to modulate the frequency within at least one blade at the blade level.

4. The method according to claim 1, wherein said circuit is a manual configuration device.

5. The method according to claim 1, wherein said circuit is a resistor.

6. The method according to claim 5, wherein said resistor is a configuration resistor.

7. The method according to claim 1, wherein said blade-based computer system utilizes multiple frequency synthesizers to generate multiple blades'"'"' clocks, wherein said blades are able to operate at different frequencies.

8. The method according to claim 1, wherein said blade-based computer system is physically partitioned.

9. The method according to claim 1, wherein said blade-based computer system is logically partitioned.

10. A method for managing the operating frequency of processors in a blade-based computer system, said method comprising the steps of:

receiving, by a circuit in said blade-based computer system, a signal, said signal comprising instructions related to said operating frequency;

generating, by said circuit, a control signal based upon a specific frequency designated by a user;

processing, by a frequency synthesizer in said blade-based computer system, an input frequency signal and said control signal; and

outputting, by said frequency synthesizer, an output frequency to be used by said individual processors in said blade-based computer system.

11. The method according to claim 10, wherein said method adjusts the frequency level of individual processors to modulate the frequency within at least one blade at the processor level.

12. The method according to claim 10, wherein said method adjusts the frequency level of at least one processor to modulate the frequency within at least one blade at the blade level.

13. The method according to claim 10, wherein said signal received by said circuit is received over an I²C bus.

14. The method according to claim 10, wherein said signal received by said circuit is received from a service processor.

15. The method according to claim 10, wherein said circuit is a microcontroller.

16. The method according to claim 10, wherein said circuit is a microprocessor.

17. The method according to claim 10, wherein said circuit is a field-programmable gate array.

18. The method according to claim 10, wherein said circuit is a programmable logic device.

19. The method according to claim 10, wherein said circuit is an I²C compatible device.

20. The method according to claim 10, wherein said circuit is an I/O expander.

21. The method according to claim 10, wherein said blade-based computer system utilizes multiple frequency synthesizers to control multiple processors'"'"' clocks, wherein said processors are able to operate at different frequencies.

22. A method for managing the operating frequency of processors in a blade-based computer system, said method comprising the steps of:

receiving, by a circuit in said blade-based computer system, a signal, said signal comprising instructions related to said operating frequency;

generating, by said circuit, a control signal, said control signal based upon the bus frequency of said blade-based computer system and a specific frequency designated by a user;

processing, by a frequency synthesizer in said blade-based computer system, said control signal; and

outputting, by said frequency synthesizer, an output frequency, said output frequency based upon a multiple of said bus frequency to be used by at least one processor.

23. The method according to claim 22, wherein said method adjusts the frequency level of individual processors to modulate the frequency within at least one blade at the processor level.

24. The method according to claim 22, wherein said method adjusts the frequency level of at least one processor to modulate the frequency within at least one blade at the blade level.

25. The method according to claim 22, wherein said circuit is the main core chipset.

26. The method according to claim 22, wherein a user interface is used to program said main core chipset to generate said control signal.

27. The method according to claim 22, wherein the bus frequency is multiplied to a larger ratio to generate a higher frequency, and said bus frequency is multiplied to a smaller ratio to generate a lower frequency depending on the application at said blade.

28. The method according to claim 22, wherein said blade-based computer system utilizes multiple frequency synthesizers to control multiple processors'"'"' clocks, wherein said blades are able to operate at different frequencies.

29. A system for managing the operating frequency of processors in a blade-based computer system, said system comprising:

an I²C device in said blade-based computer system, said I²C device receiving a signal, said signal comprising instructions related to said operating frequency;

a means for generating a control signal in said blade-based computer system based upon said instructions related to said operating frequency;

a clock generator in said blade-based computer system, said clock generator, receiving said control signal;

a means for processing an input frequency signal and said control signal from said I²C device in said blade-based computer system; and

outputting, by said clock generator, an output frequency to be used by at least one processor in said blade-based computer system.