Method and apparatus for testing physical memory in an information handling system under conventional operating systems

• US 20040068680A1
• Filed: 10/08/2002
• Published: 04/08/2004
• Est. Priority Date: 10/08/2002
• Status: Active Grant

• Current Assignee: Dell Products LP (Dell Technologies Inc.)
• Original Assignee: Dell Products LP (Dell Technologies Inc.)
• Inventors: Mohammad, Rais A.
• Granted Patent: US 7,093,166 B2
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

An information handling system includes at least one microprocessor, a physical memory coupled to the at least one microprocessor, and a physical memory testing subsystem. The physical memory is configured to store an operating system. The physical memory testing subsystem is configured for a) querying the operating system for the size of the physical memory and a number of microprocessors, b) in response to the number of microprocessors, creating memory tester threads equal in number to the number of microprocessors, c) in response to the size of the physical memory, allocating memory chunks of a virtual memory to be on the order of the size of the physical memory, d) dividing the allocated memory chunks equally among the memory tester threads, e) creating a scanner thread, and f) executing the memory tester threads and scanner thread, wherein the scanner thread is configured to increase the probability of maintaining the allocated memory in physical memory for a duration of physical memory testing by the memory tester threads.

Claims

1. An information handling system comprising:

at least one microprocessor;

a physical memory coupled to said at least one microprocessor, said physical memory configured to store an operating system; and

a physical memory testing subsystem configured for a) querying the operating system for the size of said physical memory and a number of microprocessors, b) in response to the number of microprocessors, creating memory tester threads equal in number to the number of microprocessors, c) in response to the size of said physical memory, allocating memory chunks of a virtual memory to be on the order of the size of said physical memory, d) dividing the allocated memory chunks equally among the memory tester threads, e) creating a scanner thread, and f) executing the memory tester threads and scanner thread, wherein the scanner thread is configured to increase the probability of maintaining the allocated memory in physical memory for a duration of physical memory testing by the memory tester threads.

2. The information handling system of claim 1, wherein querying the operating system includes using an API.

3. The information handling system of claim 1, wherein allocating memory chunks of the virtual memory includes configuring the virtual memory to be equal in size to the physical memory.

4. The information handling system of claim 1, wherein the information handling system includes two microprocessors, and further wherein creating memory tester threads includes using an API configured to create two memory tester threads.

5. The information handling system of claim 1, wherein said physical memory testing subsystem is further configured for iterating over all of the allocated memory chunks with the scanner thread, and repeating the iterating until testing by the memory tester threads is complete.

6. The information handling system of claim 1, wherein the memory tester threads are configured to write a pattern into a memory chunk and perform a verify operation, wherein the verify operation includes reading the pattern back from the memory chunk and comparing the read pattern with the original pattern.

7. The information handling system of claim 1, wherein said physical memory testing subsystem is further configured for iterating over all of the allocated memory chunks with the scanner thread, reading a first byte of every memory page in the chunk, and repeating the iterating of the scanner thread until a completion of testing by the tester threads.

8. The information handling system of claim 7, wherein said physical memory testing subsystem is further configured for iterating over the assigned memory chunks with a memory tester thread, writing a byte pattern into a respective memory chunk, and performing a verify operation.

9. The information handling system of claim 1, wherein said physical memory testing subsystem is further configured for iterating over the assigned memory chunks with a memory tester thread, writing a byte pattern into a respective memory chunk, and performing a verify operation.

10. The information handling system of claim 1, wherein said physical memory testing subsystem is further configured for iterating over all of the allocated memory chunks with the scanner thread, and repeating the iterating until testing by the memory tester threads is complete, wherein the memory tester threads are configured to write a pattern into a memory chunk and perform a verify operation, wherein the verify operation includes reading the pattern back from the memory chunk and comparing the read pattern with the original pattern.

11. A method for implementing physical memory testing in an information handling system having an operating system, the method comprising:

querying the operating system for the size of a physical memory and a number of CPUs;

in response to the number of CPUs, creating memory tester threads equal in number to the number of CPUs;

in response to the size of the physical memory, allocating memory chunks of a virtual memory to be on the order of the size of the physical memory;

dividing the allocated memory chunks equally among the memory tester threads;

creating a scanner thread; and

executing the memory tester threads and scanner thread, wherein the scanner thread is configured to increase the probability of maintaining the allocated memory in physical memory for a duration of physical memory testing by the memory tester threads.

12. The method of claim 11, wherein querying the operating system includes using an API.

13. The method of claim 11, wherein allocating memory chunks of the virtual memory includes configuring the virtual memory to be equal in size to the physical memory.

14. The method of claim 11, wherein the information handling system includes two CPUs, and further wherein creating memory tester threads includes using an API configured to create two memory tester threads.

15. The method of claim 11, further comprising iterating over all of the allocated memory chunks with the scanner thread, and repeating the iterating until testing by the memory tester threads is complete.

16. The method of claim 11, wherein the memory tester threads are configured to write a pattern into a memory chunk and perform a verify operation, wherein the verify operation includes reading the pattern back from the memory chunk and comparing the read pattern with the original pattern.

17. The method of claim 11, further comprising:

with the scanner thread, iterating over all of the allocated memory chunks, reading a first byte of every memory page in the chunk, and repeating the iterating of the scanner thread until a completion of testing by the tester threads.

18. The method of claim 17, further comprising:

with each memory tester thread, iterating over the assigned memory chunks, writing a byte pattern into a respective memory chunk, and performing a verify operation.

19. The method of claim 11, further comprising:

with each memory tester thread, iterating over the assigned memory chunks, writing a byte pattern into a respective memory chunk, and performing a verify operation.

20. The method of claim 11, further comprising:

iterating over all of the allocated memory chunks with the scanner thread, and repeating the iterating until testing by the memory tester threads is complete, wherein the memory tester threads are configured to write a pattern into a memory chunk and perform a verify operation, wherein the verify operation includes reading the pattern back from the memory chunk and comparing the read pattern with the original pattern.

21. A computer program for implementing physical memory testing, the computer program processable by an information handling system for causing the information handling system to:

query an operating system of the information handling system for the size of a physical memory and a number of CPUs;

create, in response to the number of CPUs, memory tester threads equal in number to the number of CPUs;

allocate, in response to the size of the physical memory, memory chunks of a virtual memory to be on the order of the size of the physical memory;

divide the allocated memory chunks equally among the memory tester threads;

create a scanner thread; and

execute the memory tester threads and scanner thread, wherein the scanner thread is configured to increase the probability of maintaining the allocated memory in physical memory for a duration of physical memory testing by the memory tester threads.

22. The computer program of claim 21, wherein querying the operating system includes using an API.

23. The computer program of claim 21, wherein allocating memory chunks of the virtual memory includes configuring the virtual memory to be equal in size to the physical memory.

24. The computer program of claim 21, further processable by the information handling system for causing the information handling system to:

iterate over all of the allocated memory chunks with the scanner thread, and repeat the iterating until testing by the memory tester threads is complete.

25. The computer program of claim 21, wherein the memory tester threads are configured to write a pattern into a memory chunk and perform a verify operation, wherein the verify operation includes reading the pattern back from the memory chunk and comparing the read pattern with the original pattern.

26. The computer program of claim 21, further processable by the information handling system for causing the information handling system to:

iterate over all of the allocated memory chunks with the scanner thread, a reading of a first byte of every memory page in the chunk, and repeating the iterating of the scanner thread until a completion of testing by the tester threads.

27. The computer program of claim 26, further processable by the information handling system for causing the information handling system to:

iterate over the assigned memory chunks with each memory tester thread, a writing of a byte pattern into a respective memory chunk, and performing a verify operation.

28. The computer program of claim 21, further processable by the information handling system for causing the information handling system to:

iterate over the assigned memory chunks with each memory tester thread, a writing of a byte pattern into a respective memory chunk, and performing a verify operation.

29. The computer program of claim 21, further processable by the information handling system for causing the information handling system to:

iterate over all of the allocated memory chunks with the scanner thread, and repeat the iterating until testing by the memory tester threads is complete, wherein the memory tester threads are configured to write a pattern into a memory chunk and perform a verify operation, wherein the verify operation includes reading the pattern back from the memory chunk and comparing the read pattern with the original pattern.