Method to test power distribution system

• US 20040068700A1
• Filed: 10/04/2002
• Published: 04/08/2004
• Est. Priority Date: 10/04/2002
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Noujeim, Leesa, Sen, Bidyut K.
• Granted Patent: US 6,925,616 B2
• Time in Patent Office: Days
• US Class Current: 716/4
• CPC Class Codes: G01R 31/31721 Power aspects, e.g. power supplies for test circuits, power saving during test for scan test G01R31/318575

Abstract

A method for testing a core power distribution system for an integrated circuit chip which includes arranging a plurality of experiments for an integrated circuit chip, performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances, generating a schmoo diagram for each of the plurality of experiments, and analyzing the schmoo diagrams to determine whether how the core power distribution system functions at a particular frequency is acceptable.

Claims

1. A method for testing a core power distribution system for an integrated circuit chip comprising:

arranging a plurality of experiments for an integrated circuit chip;

performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;

generating a schmoo diagram for each of the plurality of experiments; and

,

analyzing the schmoo diagrams to determine whether how the core power distribution system functions at a particular frequency is acceptable.

2. The method for testing a core power distribution system of claim 1 wherein

the arranging a plurality of experiments for an integrated circuit chip includes progressively depopulating pins of the integrated circuit chip.

3. The method for testing a core power distribution system of claim 2 wherein

the progressively depopulating pins includes progressively depopulating pins to generate a progressively more separate layout.

4. The method for testing a core power distribution system of claim 2 wherein

the progressively depopulating pins includes progressively depopulating pins to generate a progressively more centered layout.

5. The method for testing a core power distribution system of claim 2 wherein

the progressively depopulating pins includes progressively depopulating pins to generate a progressively more perimeter oriented layout.

6. The method for testing a core power distribution system of claim 1 wherein

the arranging a plurality of experiments for an integrated circuit chip includes at least one of replacing an integrated circuit socket with another integrated circuit socket, replacing an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit module and depopulating an integrated circuit socket.

7. The method for testing a core power distribution system of claim 1 further comprising:

repeating the performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;

generating a schmoo diagram for each of the repeated plurality of experiments; and

,

analyzing the schmoo diagrams to determine whether how the core power distribution system functions at a particular frequency is acceptable.

8. A system for testing a core power distribution system for an integrated circuit chip comprising:

means for arranging a plurality of experiments for an integrated circuit chip;

means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;

means for generating a schmoo diagram for each of the plurality of experiments; and

,

means for analyzing the schmoo diagrams to determine whether how the core power distribution system functions at a particular frequency is acceptable.

9. The system for testing a core power distribution system of claim 8 wherein

the means for arranging a plurality of experiments for an integrated circuit chip includes progressively depopulating pins of the integrated circuit chip.

10. The system for testing a core power distribution system of claim 9 wherein

the progressively depopulating pins includes progressively depopulating pins to generate a progressively more separate layout.

11. The system for testing a core power distribution system of claim 9 wherein

the progressively depopulating pins includes progressively depopulating pins to generate a progressively more centered layout.

12. The system for testing a core power distribution system of claim 9 wherein

the progressively depopulating pins includes progressively depopulating pins to generate a progressively more perimeter oriented layout.

13. The system for testing a core power distribution system of claim 8 wherein

the means for arranging a plurality of experiments for an integrated circuit chip includes at least one of replacing an integrated circuit socket with another integrated circuit socket, replacing an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit module and depopulating an integrated circuit socket.

14. The system for testing a core power distribution system of claim 8 further comprising:

means for repeating the performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;

means for generating a schmoo diagram for each of the repeated plurality of experiments; and

,

means for analyzing the schmoo diagrams to determine whether how the core power distribution system functions at a particular frequency is acceptable.

15. An apparatus for testing a core power distribution system for an integrated circuit chip via a plurality of experiments including progressively depopulating power and ground connections of the integrated circuit chip, the apparatus comprising:

means for performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;

means for generating a schmoo diagram for each of the plurality of experiments; and

,

means for analyzing the schmoo diagrams to determine whether how the core power distribution system functions at a particular frequency is acceptable.

16. The apparatus for testing a core power distribution system of claim 15 wherein

the progressively depopulating pins includes progressively depopulating pins to generate a progressively more separate layout.

17. The apparatus for testing a core power distribution system of claim 15 wherein

the progressively depopulating pins includes progressively depopulating pins to generate a progressively more centered layout.

18. The apparatus for testing a core power distribution system of claim 15 wherein

the progressively depopulating pins includes progressively depopulating pins to generate a progressively more perimeter oriented layout.

19. The apparatus for testing a core power distribution system of claim 15 wherein

the plurality of experiments for an integrated circuit chip include at least one of replacing an integrated circuit socket with another integrated circuit socket, replacing an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit chip within an integrated circuit socket, reseating an integrated circuit module and depopulating an integrated circuit socket.

20. The apparatus for testing a core power distribution system of claim 15 further comprising:

means for repeating the performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances;

means for generating a schmoo diagram for each of the repeated plurality of experiments; and

,

means for analyzing the schmoo diagrams to determine whether how the core power distribution system functions at a particular frequency is acceptable.