Method of wire bonding over active area of a semiconductor circuit

• US 20040070042A1
• Filed: 05/08/2003
• Published: 04/15/2004
• Est. Priority Date: 10/15/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megic Corporation (Chipbond Technology Corporation)
• Inventors: Lee, Jin-Yuan, Chen, Ying-chih
• Granted Patent: US 8,021,976 B2
• Time in Patent Office: Days
• US Class Current: 257/459
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05187 Ceramics, e.g. crystalline carbides, nitrides or oxides glass ceramics H01L2224/05188
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/4807 of bonding interfaces, e.g. interlocking features
• CPC Class Codes: H01L 2224/48453 of the interface with the bonding area
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48599 Principal constituent of the connecting portion of the wire connector being Gold (Au)
• CPC Class Codes: H01L 2224/48624 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/48644 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48647 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/854 : with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85447 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor

Abstract

A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.

Claims

1. A method for enabling wire bond connections over active regions of an Integrated Circuit die, comprising:

providing a semiconductor substrate having active and/or passive devices formed thereon;

providing interconnect metallization formed over said active and/or passive devices, including an upper metal layer;

providing a passivation layer formed over said interconnect metallization, wherein openings are formed in said passivation layer to said upper metal layer; and

forming compliant metal bond pads over said passivation layer, wherein said compliant metal bond pads are connected through said openings to said upper metal layer, and wherein said compliant metal bond pads are formed substantially over said active and/or passive devices.

2. The method of claim 1, wherein the compliant metal bond pads are formed to a thickness greater than about 1.5 um.

3. The method of claim 1, wherein the compliant metal bond pads are formed with a composite metal comprising at least a bulk layer of metal and an adhesion layer of metal.

4. The method of claim 3, wherein the bulk layer of metal is formed to a thickness greater than about 1 um.

5. The method of claim 3, wherein the bulk layer of metal is formed by electroplating.

6. The method of claim 3, wherein the bulk layer of metal is Au, Cu, Sn, Pb-alloy, Sn-alloy, AgSn alloy or AgCuSn alloy.

7. The method of claim 1, wherein the compliant metal bond pads are formed over said openings.

8. The method of claim 1, wherein the compliant metal bond pads are laterally displaced from one or more of said openings.

9. The method of claim 1 wherein each of said openings is formed to a minimum width of about 0.1 μ

m.

10. The method of claim 1, further comprising an intermetal dielectric formed over said die, and between metal layers of said interconnect metallization, wherein said intermetal dielectric is a low-k dielectric.

11. The method of claim 1, wherein said passivation layer comprises one or more layers of inorganic material.

12. The method of claim 1, further comprising forming a glue/barrier layer under said compliant metal bond pads, and over said passivation layer.

13. The method of claim 12, wherein the glue/barrier layer is Ti, Cr, TiW or TiN.

14. The method of claim 12, wherein said glue/barrier layer is formed to a thickness of about 3000 Angstroms.

15. The method of claim 1, wherein the compliant metal bond pad comprises a bulk Au layer having a hardness range of less than about 150 Hv, an Au purity larger than about 97%, and a thickness larger than about 1 μ

m.

16. The method of claim 1, wherein the compliant metal bond pad comprises a bulk Au layer, and wherein the bulk Au layer is annealed at a temperature of between about 120°

C. and 350°

C.

17. The method of claim 1, wherein the compliant metal bond pad comprises a bulk Au layer, and wherein the bulk Au layer is annealed in an N₂ ambient.

18. The method of claim 15, further comprising forming a Au seed layer over said glue/barrier layer, to a thickness of about 1000 Angstroms.

19. The method of claim 1, further comprising forming an organic layer between said compliant metal bond pads and the passivation layer.

20. The method of claim 19, wherein the organic layer is formed by spin coating photosensitive material, followed by photolithographic exposure, development and curing.

21. The method of claim 19 wherein the organic layer is formed by screen printing and curing.

22. The method of claim 19, wherein the organic layer comprises polyimide, benzocyclobutene (BCB), elastomers, silicone or parylene.

23. The method of claim 1, further comprising forming one or more power/ground plane and/or I/O signal lines over said passivation layer, formed of the same material as is used to form said bond pad.

24. The method of claim 1, wherein the layer of compliant metal comprises a Au seed layer formed over a glue/barrier layer, deposited over the layer of passivation, and a Au layer formed over the Au seed layer.

25. The method of claim 1, wherein each of said compliant metal bond pads is connected to said upper metal layer through one or more of said openings through said passivation layer.

26. The method of claim 1, wherein each of said compliant metal bond pads is connected to said upper metal layer through more than one of said openings through said passivation layer.

27. The method of claim 1, wherein each of said compliant metal bond pads is connected to said upper metal layer through a single one of said openings through said passivation layer.

28. A method for enabling wire bond connections over active regions of a Integrated Circuit die, comprising:

providing a semiconductor substrate having active and/or passive devices formed thereon;

providing interconnect metallization formed over said active and/or passive devices, including an upper metal layer;

providing a passivation layer formed over said interconnect metallization, wherein openings are formed in said passivation layer to said upper metal layer;

depositing a glue/barrier layer over said passivation layer and in said openings;

depositing an electroplating seed layer over said glue/barrier layer;

depositing photoresist over said substrate and forming bond pad openings in said photoresist;

forming compliant metal bond pads in said bond pad openings by electroplating;

removing said photoresist; and

removing said electroplating seed layer and said glue/barrier layer in regions outside of said compliant metal bond pads, using said compliant metal bond pads as a mask,

wherein said compliant metal bond pads are connected through said passivation openings to said upper metal layer, and wherein said compliant metal bond pads are formed substantially over said active and/or passive devices.

29. The method of claim 28, wherein the glue/barrier layer is Ti, Cr, TiW or TiN.

30. The method of claim 28, wherein the compliant metal bond pads, and said electroplating seed layer, are formed of gold.

31. The method of claim 28, wherein the compliant metal bond pads are formed by electroplating a bulk Cu layer over said electroplating seed layer, electroplating a Ni layer over said bulk Cu layer, and electroplating a wire bondable Au layer over said Ni layer.

32. The method of claim 31, wherein said bulk Cu layer is formed to a thickness larger than about 1 μ

m.

33. The method of claim 31, wherein said Ni layer is formed to a thickness larger than about 0.5 μ

m.

34. The method of claim 31, wherein said Ni layer is formed to a thickness of between about 1 and 5 μ

m.

35. The method of claim 31, wherein the layer of wire bondable Au is formed to a thickness larger than about 100 Angstroms.

36. The method of claim 33, wherein the compliant metal bond pads are formed by electroplating a bulk copper layer in said bond pad openings, over said electroplating seed layer, and electroplating a wire bondable Au layer over said bulk copper layer.

37. The method of claim 36, wherein the bulk copper layer is formed to a thickness larger than about 1 μ

m.

38. The method of claim 36, wherein the layer of wire bondable Au is formed to a thickness larger than about 100 Angstroms.

39. The method of claim 28, wherein the compliant metal bond pads are formed by electroplating solder in said bond pad openings, over said electroplating seed layer, and electroplating a wire bondable Au layer over said solder.

40. The method of claim 39, wherein said solder is a Pb alloy, Sn, Sn alloy, AgSn alloy or AgCuSn alloy.

41. The method of claim 40 wherein the electroplating seed layer comprises Cu or Ni.

42. The method of claim 40, wherein the solder is formed to a thickness larger than about 1.0 μ

m.

43. The method of claim 40, wherein the layer of wire bondable Au is formed to a thickness larger than about 100 Angstroms.

44. The method of claim 28, wherein each of said compliant metal bond pads is connected to said upper metal layer through one or more of said openings through said passivation layer.

45. The method of claim 28 wherein each of said compliant metal bond pads is connected to said upper metal layer through more than one of said openings through said passivation layer.

46. The method of claim 28 wherein each of said compliant metal bond pads is connected to said upper metal layer through a single one of said openings through said passivation layer.

47. A structure for connecting devices on a semiconductor die to an external package using wire bonds, comprising:

a semiconductor substrate having active and/or passive devices formed thereon;

interconnect metallization formed over said active and/or passive devices, including an upper metal layer;

a passivation layer formed over said interconnect metallization, wherein openings are formed in said passivation layer to said upper metal layer; and

composite metal bond pads formed over said passivation layer, wherein said composite metal bond pads are connected through said openings to said upper metal layer, and wherein said composite metal bond pads are formed substantially over said active and/or passive devices.

48. The structure of claim 47, wherein the composite metal bond pads have a thickness greater than about 1.5 um.

49. The structure of claim 47 wherein the composite metal bond pads comprise at least a bulk layer of metal and an adhesion layer of metal.

50. The structure of claim 47, wherein the composite metal bond pads comprise at least an adhesion layer at bottom, a bulk layer over the adhesion layer, and a wirebondable metal layer on top.

51. The structure of claim 50, wherein the bulk layer has a thickness greater than about 1 um.

52. The structure of claim 50, wherein the bulk layer is Cu, Ni, Sn, SnPb alloy, AgSn alloy, AgCuSn alloy.

53. The structure of claim 50, wherein the adhesion layer is Ti, TiW, TiN, or Cr.

54. The structure of claim 50, wherein the wirebondable layer is formed of Au or Al.

55. The structure of claim 47, wherein wire bonding regions of said composite metal bond pads are laterally displaced from one or more of said openings in said passivation layer.

56. The structure of claim 47, wherein wire bonding regions of said composite metal bond pads are formed over one or more of said openings in said passivation layer.

57. The structure of claim 47, wherein said composite metal bond pads are formed of a Cu/Ni/Au composite, wherein said Cu layer is a bottom layer of said Cu/Ni/Au composite.

58. The structure of claim 57 wherein said composite metal bond pads are formed over a Cu seed layer, wherein said Cu layer forms a bulk layer, and said Ni layer is a diffusion barrier.

59. The structure of claim 58, wherein said Cu layer is formed to a thickness larger than about 1 μ

m.

60. The structure of claim 58, wherein said Ni layer is formed to a thickness larger than about 0.5 μ

m.

61. The structure of claim 58, wherein said Ni layer is formed to a thickness of between about 1 and 5 μ

m.

62. The structure of claim 58, wherein said Au layer is wire bondable Au and is formed to a thickness larger than about 100 Angstroms.

63. The structure of claim 47, wherein said composite metal bond pads are formed of a Cu/Au composite, wherein said Cu layer is a bottom layer of said Cu/Au composite, and wherein said Cu layer is a bulk layer.

64. The structure of claim 63 wherein said composite metal bond pads are formed over a Cu seed layer.

65. The structure of claim 63, wherein said Cu layer is formed to a thickness larger than about 1 μ

m.

66. The structure of claim 63, wherein said Au layer is wire bondable Au and is formed to a thickness larger than about 100 Angstroms.

67. The structure of claim 47, wherein said composite metal bond pads are formed of a solder/Au composite, wherein said solder layer is a bottom layer of said solder/Au composite,

68. The structure of claim 67, wherein said composite metal bond pads are formed over a seed layer formed of Cu or Ni.

69. The structure of claim 68, wherein said solder layer is a Pb alloy, Sn, Sn alloy, AgSn alloy or AgCuSn alloy.

70. The structure of claim 67, wherein the solder is formed to a thickness larger than about 1.0 μ

m.

71. The structure of claim 47, wherein said openings formed in said passivation layer have a minimum width of about 0.1 μ

m.

72. The structure of claim 47, further comprising an intermetal dielectric formed over said semiconductor substrate, wherein said intermetal dielectric is a low-k dielectric.

73. The structure of claim 47, wherein said passivation layer comprises one or more layers of inorganic material.

74. The structure of claim 47, further comprising a glue/barrier layer under said composite metal bond pads.

75. The structure of claim 74, wherein the glue/barrier layer is Ti, Cr, TiW or TiN.

76. The structure of claim 74, wherein the glue/barrier layer is formed over the layer of passivation and in said openings in said passivation layer.

77. The structure of claim 47, further comprising an organic layer between the composite metal bond pads and the passivation layer.

78. The structure of claim 77, wherein the organic layer comprises polyimide, benzocyclobutene (BCB), elastomers, silicone or parylene.

79. The structure of claim 47, further comprising one or more power/ground plane and I/O signal lines formed over said passivation layer and formed of the same material as is used to form said bond pad.

80. The structure of claim 47, wherein each of said compliant metal bond pads is connected to said upper metal layer through one or more of said openings through said passivation layer.

81. The structure of claim 47, wherein each of said compliant metal bond pads is connected to said upper metal layer through more than one of said openings through said passivation layer.

82. The structure of claim 47, wherein each of said compliant metal bond pads is connected to said upper metal layer through a single one of said openings through said passivation layer.

83. A structure for connecting devices on a semiconductor die to an external package using wire bonds, comprising:

a semiconductor substrate having active and/or passive devices formed thereon;

interconnect metallization formed over said active and/or passive devices, including an upper metal layer;

a passivation layer formed over said interconnect metallization, having first openings to said upper metal layer;

an organic layer formed over said passivation layer, having second openings, over said first openings, to said upper metal layer; and

gold bond pads formed over said organic layer, wherein said gold bond pads are connected through said first and second openings to said upper metal layer, and wherein said gold bond pads are formed substantially over said active and/or passive devices.

84. A structure for connecting devices on a semiconductor die to an external package using wire bonds, comprising:

a semiconductor substrate having active and/or passive devices formed thereon;

interconnect metallization formed over said active and/or passive devices, including an upper metal layer;

a passivation layer formed over said interconnect metallization, wherein openings are formed in said passivation layer to said upper metal layer; and

composite metal bond pads formed over said passivation layer, wherein said composite metal bond pads are connected through said openings to said upper metal layer,

wherein said composite metal bond pads are formed substantially over said active and/or passive devices; and

wherein each said composite metal bond pad is connected to said upper metal layer through multiple said openings in said passivation layer.

85. The structure of claim 84 wherein each said composite metal bond pad is connected to a single contact pad in said upper metal layer, through the multiple said openings.

86. The structure of claim 84, further comprising a wire bond connected to each said metal bond pad, wherein said wire bond is located over the multiple said openings.

87. The structure of claim 84 wherein each said composite metal bond pad is connected to multiple contact pads in said upper metal layer, through the multiple said openings.

88. The structure of claim 87, further comprising a wire bond connected to each said metal bond pad, wherein said wire bond is located over the multiple said openings.

89. The structure of claim 84 further comprising an organic layer between the composite metal bond pads and the passivation layer, wherein said organic layer has second openings over said passivation layer openings, and wherein said composite metal bond pads are connected through said first and second openings to said upper metal layer.

90. The structure of claim 89 wherein each said composite metal bond pad is connected to a single contact pad in said upper metal layer, through said multiple openings.

91. The structure of claim 90, further comprising a wire bond connected to each said metal bond pad, wherein said wire bond is located over the multiple said openings.

92. The structure of claim 89 wherein each said composite metal bond pad is connected to multiple contact pads in said upper metal layer, through said multiple openings.

93. The structure of claim 92, further comprising a wire bond connected to each said metal bond pad, wherein said wire bond is located over the multiple said openings.

94. A method for enabling wire bond connections over low-k dielectric layers formed on an Integrated Circuit die, comprising:

providing a semiconductor substrate having at least one low-K dielectric layer formed thereover;

providing interconnect metallization formed over said low-K dielectric layer, including an upper metal layer;

providing a passivation layer formed over said interconnect metallization, wherein openings are formed in said passivation layer to said upper metal layer; and

forming compliant metal bond pads over said passivation layer, wherein said compliant metal bond pads are connected through said openings to said upper metal layer, and wherein said compliant metal bond pads are formed substantially over said low-K dielectric layer.

95. The method of claim 94, wherein the compliant metal bond pads are formed to a thickness greater than about 1.5 um.

96. The method of claim 94, wherein the compliant metal bond pads are formed with a composite metal comprising at least a bulk layer of metal and an adhesion layer of metal.

97. The method of claim 96, wherein the bulk layer of metal is formed to a thickness greater than about 1 um.

98. The method of claim 96, wherein the bulk layer of metal is formed by electroplating.

99. The method of claim 96, wherein the bulk layer of metal is Au, Cu, Sn, Pb-alloy, Sn-alloy, AgSn alloy or AgCuSn alloy.

100. The method of claim 94, wherein the compliant metal bond pads are formed over said openings.

101. The method of claim 94, wherein the compliant metal bond pads are laterally displaced from one or more of said openings.

102. The method of claim 94 wherein each of said openings is formed to a minimum width of about 0.1 μ

m.

103. The method of claim 94, further comprising forming an organic layer between the compliant metal bond pads and the passivation layer.

104. The method of claim 103, wherein the organic layer comprises polyimide, benzocyclobutene (BCB), elastomers, silicone or parylene.

105. A structure for connecting devices on a semiconductor die to an external package using wire bonds, comprising:

a semiconductor substrate having at least one low-K dielectric layer formed thereover;

interconnect metallization formed over said low-K dielectric layer, including an upper metal layer;

a passivation layer formed over said interconnect metallization, wherein openings are formed in said passivation layer to said upper metal layer; and

composite metal bond pads formed over said passivation layer, wherein said composite metal bond pads are connected through said openings to said upper metal layer, and wherein said composite metal bond pads are formed substantially over said low-K dielectric layer.

106. The structure of claim 105, wherein the composite metal bond pads have a thickness greater than about 1.5 um.

107. The structure of claim 105 wherein the composite metal bond pads comprise at least a bulk layer of metal and an adhesion layer of metal.

108. The structure of claim 105, wherein the composite metal bond pads comprise at least an adhesion layer at bottom, a bulk layer over the adhesion layer, and a wirebondable metal layer on top.

109. The structure of claim 108, wherein the bulk layer has a thickness greater than about 1 um.

110. The structure of claim 105, further comprising an organic layer between the composite bond pads and the passivation layer.

111. The structure of claim 110, wherein the organic layer comprises polyimide, benzocyclobutene (BCB), elastomers, silicone or parylene.