Semiconductor device and method of manufacturing substrate

• US 20040070051A1
• Filed: 07/02/2003
• Published: 04/15/2004
• Est. Priority Date: 12/24/1998
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Tezuka, Tsutomu, Kurobe, Atsushi, Takagi, Shinichi, Sugiyama, Naoharu, Mizuno, Tomohisa
• Granted Patent: US 6,917,096 B2
• Time in Patent Office: Days
• US Class Current: 257/616
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0245 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02664 Aftertreatments planarisation in general H01L21/304
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/31675 of silicon
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/7848 : the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/78687 : with a multilayer structure or superlattice structure
• CPC Class Codes: Y10S 438/938 : Lattice strain control or utilization

Abstract

A semiconductor device comprises a base substrate, a silicon oxide layer formed on the base substrate, a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %, a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer, a gate electrode configured to induce a channel in a surface region of the second semiconductor layer, and a gate insulating film formed between the second semiconductor layer and the gate electrode.

Claims

1. A semiconductor device comprising:

a base substrate;

a silicon oxide layer formed on the base substrate;

a first semiconductor layer formed on the silicon oxide layer, the first semiconductor layer including an SiGe layer with a Ge concentration not less than 30 atomic %;

a second semiconductor layer formed on the first semiconductor layer, the second semiconductor layer including a Ge layer or an SiGe layer with a Ge concentration higher than the first semiconductor layer;

a gate electrode configured to induce a channel in a surface region of the second semiconductor layer; and

a gate insulating film formed between the second semiconductor layer and the gate electrode.

2. The semiconductor device according to claim 1, wherein the first semiconductor layer is relaxed and the second semiconductor layer is strained.

3. The semiconductor device according to claim 1, wherein the gate insulating film is formed on an upper surface of the second semiconductor layer.

4. The semiconductor device according to claim 3, wherein the second semiconductor layer includes both a source region and a drain region.

5. The semiconductor device according to claim 1, wherein the gate insulating film is formed on a side surface of the second semiconductor layer.

6. The semiconductor device according to claim 5, further comprising a third semiconductor layer formed on an upper surface of the second semiconductor layer, wherein the first semiconductor layer includes one of a source region and a drain region and the third semiconductor layer includes the other of the source region and the drain region.

7. The semiconductor device according to claim 1, wherein a dislocation density of the first semi-conductor layer is not greater than 10⁶ cm⁻

2.

8. The semiconductor device according to claim 1, wherein a distribution of Ge atoms contained in the first semiconductor layer is uniform in a depth direction.

9. The semiconductor device according to claim 1, further comprising an Si layer formed between the second semiconductor layer and the gate insulating film.

10. A method of manufacturing a substrate comprising:

forming a laminated layer including a layer containing silicon and oxygen and an SiGe layer, the layer containing silicon and oxygen being located between the base substrate and the SiGe layer; and

oxidizing the SiGe layer to form a silicon oxide layer and to increase a Ge concentration of the SiGe layer.

11. The method according to claim 10, wherein a thickness of the SiGe layer is reduced after the oxidizing.

12. The method according to claim 10, wherein the oxidizing is a thermal treatment in an oxidizing atmosphere.

13. The method according to claim 10, wherein the layer containing silicon and oxygen is an amorphous layer.

14. The method according to claim 10, wherein the layer containing silicon and oxygen is a crystal silicon layer containing oxygen.

15. The method according to claim 10, wherein the layer containing silicon and oxygen further contains germanium.

16. The method according to claim 10, wherein the laminated layer further includes an Si layer located between the layer containing silicon and oxygen and the SiGe layer.

17. The method according to claim 10, further comprising:

removing the silicon oxide layer on the SiGe layer after the oxidizing to expose a surface of the SiGe layer; and

forming a semiconductor layer on the exposed surface of the SiGe layer.

18. The method according to claim 10, further comprising forming a semiconductor layer on the SiGe layer after the oxidizing, the semiconductor layer including a Ge layer or an SiGe layer showing a Ge concentration higher than the SiGe layer after the oxidizing.

19. The method according to claim 10, further comprising forming a semiconductor layer on the SiGe layer after the oxidizing, the semiconductor layer including a strained crystal Si layer.

20. The method according to claim 19, further comprising forming a MISFET using the strained crystal Si layer as a channel layer.