Integrated circuit and process for fabricating the same

• US 20040070312A1
• Filed: 10/10/2002
• Published: 04/15/2004
• Est. Priority Date: 10/10/2002
• Status: Abandoned Application

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Talin, Albert Alec, Finder, Jeffrey M., Penunuri, David, Voight, Steven, Smith, Steven M., Eisenbeiser, Kurt W.
• Application Number:
  US10/267,817
• Publication Number:
  US 20040070312A1
• Time in Patent Office: Days
• US Class Current: 310/313A
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02513 Microstructure
• CPC Class Codes: H01L 21/02521 Materials
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03H 3/08 for the manufacture of resonators or networks using surface acoustic waves
• CPC Class Codes: H03H 9/02566 of semiconductor substrates
• CPC Class Codes: H03H 9/0542 consisting of a lateral arrangement H03H9/0566 takes precedence
• CPC Class Codes: H10N 39/00 Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00

Abstract

High quality epitaxial layers of monocrystalline piezoelectric materials and compound semiconductor materials can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer (28) of silicon oxide. An integrated circuit including at least one surface acoustic wave device can be formed in and over the high quality epitaxial layers.

Claims

1. An apparatus comprising:

a monocrystalline silicon substrate;

an amorphous oxide material overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide material overlying the amorphous oxide material;

a monocrystalline piezoelectric material overlying the monocrystalline perovskite oxide material; and

a surface acoustic wave device located in and over the monocrystalline piezoelectric material.

2. The apparatus of claim 1 further comprising:

a monocrystalline compound semiconductor material located under the monocrystalline piezoelectric material.

3. The apparatus of claim 1 further comprising:

a monocrystalline compound semiconductor material located over the monocrystalline piezoelectric material.

4. The apparatus of claim 1 further comprising:

a silicon semiconductor component located in and over the monocrystalline silicon substrate; and

an interconnect structure coupling the silicon semiconductor component and the surface acoustic wave device.

5. The apparatus of claim 3 further comprising:

a silicon semiconductor component located in and over the monocrystalline silicon substrate; and

an interconnect structure coupling the silicon semiconductor component and the surface acoustic wave device.

6. The apparatus of claim 3 further comprising:

a compound semiconductor component located in the monocrystalline compound semiconductor material; and

an interconnect structure coupling the compound semiconductor component and the surface acoustic wave device.

7. The apparatus of claim 1 wherein:

the monocrystalline silicon substrate has a recess; and

the monocrystalline piezoelectric material is located in the recess.

8. The apparatus of claim 7 wherein:

the monocrystalline silicon substrate has a first surface;

the recess is located in the first surface;

the monocrystalline piezoelectric material has a second surface; and

the second surface is substantially planar with the first surface.

9. The apparatus of claim 8 wherein:

the monocrystalline compound semiconductor material is located under the monocrystalline piezoelectric material.

10. The apparatus of claim 8 wherein:

the monocrystalline compound semiconductor material is located over the monocrystalline piezoelectric material.

11. The apparatus of claim 2 wherein:

the monocrystalline silicon substrate has a recess; and

the monocrystalline compound semiconductor material is located in the recess.

12. The apparatus of claim 3 wherein:

the monocrystalline silicon substrate has a recess; and

the monocrystalline compound semiconductor material is located in the recess.

13. The apparatus of claim 11 wherein:

the monocrystalline silicon substrate has a first surface;

the recess is located in the first surface;

the monocrystalline compound semiconductor material has a second surface; and

the second surface is substantially planar with the first surface.

14. The apparatus of claim 12 wherein:

the monocrystalline silicon substrate has a first surface;

the recess is located in the first surface;

the monocrystalline compound semiconductor material has a second surface; and

the second surface is substantially planar with the first surface.

15. An apparatus comprising:

a monocrystalline silicon substrate;

an amorphous oxide layer overlying the monocrystalline silicon substrate;

a monocrystalline perovskite oxide layer overlying the amorphous oxide layer;

a monocrystalline ferroelectric and piezoelectric layer overlying the monocrystalline perovskite oxide layer; and

a surface acoustic wave device located in and over the monocrystalline ferroelectric and piezoelectric layer.

16. The integrated circuit of claim 15 further comprising:

a plurality of silicon semiconductor components located in and over the monocrystalline silicon substrate; and

an interconnect structure electrically coupling together the plurality of silicon semiconductor components and the surface acoustic wave device.

17. The integrated circuit of claim 15 wherein:

the monocrystalline silicon substrate has a recess; and

the monocrystalline ferroelectric and piezoelectric layer is located in the recess.

18. The integrated circuit of claim 17 wherein:

the monocrystalline silicon substrate has a first surface;

the recess is located in the first surface;

the monocrystalline ferroelectric and piezoelectric layer has a second surface; and

the second surface is substantially planar with the first surface.

19. The integrated circuit of claim 15 further comprising:

a monocrystalline compound semiconductor layer overlying the monocrystalline perovskite oxide layer.

20. The integrated circuit of claim 19 wherein:

the monocrystalline silicon substrate has a recess; and

the monocrystalline compound semiconductor layer is located in the recess.

21. The integrated circuit of claim 20 wherein:

the monocrystalline silicon substrate has a first surface;

the recess is located in the first surface;

the monocrystalline compound semiconductor layer has a second surface; and

the second surface is substantially planar with the first surface.

22. The integrated circuit of claim 20 wherein:

the monocrystalline silicon substrate has a different recess; and

the monocrystalline ferroelectric and piezoelectric layer is located in the different recess.

23. The integrated circuit of claim 22 wherein:

the monocrystalline silicon substrate has a first surface;

the recess and the different recess are located in the first surface;

the monocrystalline ferroelectric and piezoelectric layer has a second surface;

the monocrystalline compound semiconductor layer has a third surface; and

the first, second, and third surfaces are substantially planar with each other.

24. The integrated circuit of claim 23 further comprising:

a plurality of compound semiconductor components located in the compound semiconductor layer; and

an interconnect structure electrically coupling together the plurality of compound semiconductor components and the surface acoustic wave device.

25. A process for fabricating an integrated circuit comprising:

providing a monocrystalline silicon substrate;

depositing a monocrystalline perovskite oxide layer overlying the monocrystalline silicon substrate;

forming an amorphous oxide interface layer containing at least silicon and oxygen at an interface between the monocrystalline perovskite oxide layer and the monocrystalline silicon substrate;

forming a monocrystalline piezoelectric layer overlying the monocrystalline perovskite oxide layer; and

forming a surface acoustic wave device located in and over the monocrystalline piezoelectric layer

26. The process of claim 25 further comprising:

a monocrystalline compound semiconductor layer located under the monocrystalline piezoelectric layer.

27. The process of claim 25 further comprising:

a monocrystalline compound semiconductor layer located over the monocrystalline piezoelectric layer.

28. The process of claim 25 further comprising:

forming a silicon semiconductor component located in and over the monocrystalline silicon substrate; and

forming an interconnect structure coupling together the silicon semiconductor component and the surface acoustic wave device.

29. The process of claim 27 further comprising:

forming a silicon semiconductor component located in and over the monocrystalline silicon substrate; and

forming an interconnect structure coupling together the silicon semiconductor component and the surface acoustic wave device.

30. The process of claim 27 further comprising:

forming a compound semiconductor component located in the monocrystalline compound semiconductor material; and

forming an interconnect structure coupling together the compound semiconductor component and the surface acoustic wave device.

31. The process of claim 25 further comprising:

forming a recess in the monocrystalline silicon substrate,

wherein;

forming the monocrystalline piezoelectric layer further comprises;

forming the monocrystalline piezoelectric layer in the recess.

32. The process of claim 31 wherein:

the monocrystalline silicon substrate has a first surface;

the recess is located in the first surface;

the monocrystalline piezoelectric layer has a second surface; and

the second surface is substantially planar with the first surface.

33. The process of claim 32 wherein:

a monocrystalline compound semiconductor layer is located under the monocrystalline piezoelectric layer.

34. The process of claim 32 wherein:

a monocrystalline compound semiconductor layer is located over the monocrystalline piezoelectric layer.

35. The process of claim 33 wherein:

the monocrystalline silicon substrate has a recess; and

the monocrystalline compound semiconductor layer is located in the recess.

36. The process of claim 34 wherein:

the monocrystalline silicon substrate has a recess; and

the monocrystalline compound semiconductor layer is located in the recess.

37. The process of claim 36 wherein:

the monocrystalline silicon substrate has a first surface;

the recess is located in the first surface;

the monocrystalline compound semiconductor layer has a second surface; and

the second surface is substantially planar with the first surface.

38. The process of claim 36 wherein:

the monocrystalline silicon substrate has a first surface;

the recess is located in the first surface;

the monocrystalline compound semiconductor layer has a second surface; and

the second surface is substantially planar with the first surface.