Digital adaptive sensorless commutational drive controller for a brushless DC motor

• US 20040070356A1
• Filed: 10/07/2003
• Published: 04/15/2004
• Est. Priority Date: 06/13/2002
• Status: Active Grant

• Current Assignee: Halliburton Energy Services Incorporated (Halliburton Company)
• Original Assignee: Halliburton Energy Services Incorporated (Halliburton Company)
• Inventors: Masino, James E.
• Granted Patent: US 7,030,582 B2
• Time in Patent Office: Days
• US Class Current: 318/439
• CPC Class Codes: H02P 6/12 Monitoring commutation; Providing indication of commutation failure
• CPC Class Codes: H02P 6/15 Controlling commutation time
• CPC Class Codes: H02P 6/16 Circuit arrangements for detecting position
• CPC Class Codes: H02P 6/182 using back-emf in windings
• CPC Class Codes: H02P 6/20 Arrangements for starting H02P6/08 takes precedence
• CPC Class Codes: H02P 6/30 Arrangements for controlling the direction of rotation H02P6/22 takes precedence

Abstract

Devices and methods for controlling brushless, sensorless DC motors are disclosed. In one embodiment, an electrical motor is provided with a rotor, a stator, and a semiconductor on insulator (SOI) application-specific integrated circuit (ASIC). The ASIC is configured to energize stator windings in a commutational sequence to drive the rotor. A motor controller embodiment is provided with a set of comparators and a clocked digital circuit. Each comparator determines a voltage polarity on a respective stator winding. The clocked digital circuit receives polarity signals from the comparators and detects zero crossings having an expected crossing direction, which are then used to determine a commutational sequence for energizing stator windings. A method embodiment is provided for driving DC motor windings. One method embodiment includes: receiving polarity signals, measuring intervals, and advancing a commutation state.

Claims

1. An electrical motor that comprises:

a rotor having multiple magnetic poles;

a stator having multiple windings configurable to exert a torque on the rotor when energized in a commutational sequence; and

a semiconductor on insulator (SOI) application-specific integrated circuit (ASIC) coupled to the windings of the stator and configured to apply the commutational sequence.

2. The motor of claim 1, wherein the SOI ASIC comprises a digital motor controller that senses back electromagnetic force (EMF) polarity on undriven windings of the stator to determine the commutational sequence using a state machine that is driven by a clock, and wherein the motor is operable over a range of frequencies for the clock.

3. The motor of claim 1, wherein the SOI ASIC is configured to receive signals indicative of back EMF polarity on undriven windings of the stator to perform directional zero crossing detection, and wherein the SOI ASIC determines the commutational sequence based on only those zero crossings that occur in an anticipated direction.

4. The motor of claim 1, wherein the SOI ASIC includes:

a first counter configured to count a number of cycles of a clock signal between zero crossings of back EMF signals on adjacent windings of the stator; and

a second counter configured to receive said number count from the first counter, and further configured to determine a commutation event by counting to or from said number at twice the rate of the first counter.

5. The motor of claim 4, wherein the second counter is also configured to generate a commutation event whenever an overflow occurs.

6. The motor of claim 1, wherein the SOI ASIC includes one or more limit inputs configured to halt advancement of the commutational sequence in a predetermined direction.

7. The motor of claim 6, wherein the SOI ASIC further includes a direction input to indicate whether the commutational sequence should be advance in a forward or reverse direction when a commutation event occurs.

8. A brushless DC motor controller that comprises:

a set of comparators each configured to determine a voltage polarity on a respective winding of a stator;

a clocked digital circuit configured to receive polarity signals from the comparators, configured to detect in the polarity signals zero crossings having an expected crossing direction, and configured to determine a commutational sequence for energizing windings on the stator.

9. The controller of claim 8, wherein the clocked digital circuit is implemented using semiconductor on insulator (SOI) construction.

10. The controller of claim 8, wherein the clocked digital circuit samples a polarity signal before a lockout period and compares the sample to the polarity signal after the lockout ends, and wherein the clocked digital circuit generates a zero crossing indication if the sample does not match the polarity signal after the lockout ends.

11. The controller of claim 8, wherein the clocked digital circuit includes:

a first counter configured to count a number of cycles of a clock signal between detected zero crossings of the polarity signals; and

a second counter configured to receive a count from the first counter and to count down from said count at approximately twice the rate of the clock signal, and

wherein the clocked digital circuit is configured to advance the commutational sequence when the second counter rolls over.

12. The controller of claim 8, wherein the clocked digital circuit accepts one or more limit inputs and is configured to inhibit advancement of the commutational sequence in a direction associated with the limit signal.

13. A method of driving windings in a DC motor, the method comprising:

receiving with a clocked digital circuit, polarity signals indicative of whether voltages on windings of the DC motor exceed a threshold voltage, wherein the clocked digital circuit is configured to operate in temperatures exceeding 150°

C.;

measuring intervals between transitions of the polarity signals in predicted directions; and

advancing a commutation state at a delay of some fraction of measured intervals after transitions of the polarity signals.

14. The method of claim 13, wherein said fraction is approximately one half, and wherein the measured intervals used to determine the delay are the intervals measured immediately preceding each advancement of the commutation state.

15. The method of claim 13, wherein the clocked digital circuit comprises semiconductor on insulator (SOI) circuitry.

16. The method of claim 13, further comprising:

receiving with the clocked digital circuit a direction signal indicative of a desired motor direction, and one or more limit signals each associated with a respective motor direction; and

inhibiting advancement of the commutation state if a limit signal that is associated with a direction indicated by the direction signal is asserted.

17. The method of claim 13, wherein said measuring intervals is performed with a counter operating at a first clock rate, and wherein said delay is determined by a second counter operating at a second clock rate that is greater than the first.

18. The method of claim 17, wherein said advancing a commutation state occurs when the second counter rolls over.

19. A method of applying a commutating sequence of voltages to windings of a DC motor, the method comprising:

obtaining a first sample of a polarity signal that is indicative of whether a voltage on a winding of a DC motor exceeds a threshold voltage;

advancing the commutating sequence;

obtaining a second sample of the polarity signal following a predetermined delay after said advancing;

asserting a transition detection signal if the first and second samples are different;

otherwise, sampling the polarity signal until a transition is detected and then asserting a transition detection signal; and

advancing the commutating sequence following an adaptive delay after the asserting of the transition detection signal.

20. The method of claim 19, wherein the adaptive delay is about half of a interval measured between immediately preceding assertions of the transition detection signal.

21. An integrated device that comprises:

a processor core; and

an integrated motor controller coupled to the processor core by an internal bus.

22. The device of claim 21, where the integrated motor controller is configured to sense back electromagnetic force (EMF) polarity on undriven windings of a DC motor to determine a commutational sequence using a state machine that is driven by a clock, and wherein the motor is operable over a range of frequencies for the clock.

23. The device of claim 21, wherein the integrated motor controller is configured to receive signals indicative of back EMF polarity on undriven windings of a DC motor to perform directional zero crossing detection, and wherein the integrated motor controller determines a commutational sequence based on only those zero crossings that occur in an anticipated direction.

24. The device of claim 21, wherein the integrated motor controller includes:

a first counter configured to count a number of cycles of a clock signal between zero crossings of back EMF signals on adjacent windings of a DC motor; and

a second counter configured to receive said number count from the first counter, and further configured to determine a commutation event by counting to or from said number at twice the rate of the first counter.

25. The device of claim 24, wherein the second counter is also configured to generate a commutation event whenever an overflow occurs.

26. The device of claim 21, wherein the integrated motor controller includes one or more limit inputs configured to halt advancement of a commutational sequence in a predetermined direction.

27. The device of claim 26, wherein the integrated motor controller further includes a direction input to indicate whether the commutational sequence should be advance in a forward or reverse direction when a commutation event occurs.