Bulk node biasing method and apparatus

• US 20040070441A1
• Filed: 10/10/2002
• Published: 04/15/2004
• Est. Priority Date: 10/10/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Bringivijayaraghavan, Venkatraghavan
• Granted Patent: US 6,965,263 B2
• Time in Patent Office: Days
• US Class Current: 327/534
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A biasing circuit with application to a charge pump environment for coupling the appropriate terminal voltage potentials to the bulk node. Specifically, a pass gate, such as a transistor of an integrated circuit, operates to isolate a boosted voltage input from a boosting device such as a charge pump voltage doubler and to transfer or pass the related charge to an output that is coupled to a charge store. The input and output of the pass gate are subjected to variations in voltage levels creating transient voltage potential relationships between the input (e.g., source), the output (e.g., drain), and the pass gate substrate (e.g., bulk node). Such fluctuations are accommodated through continuous monitoring of the input and output terminals and, when appropriate, coupling the corresponding potential as exhibited at one of the input or output terminals to the substrate or bulk node of the pass gate.

Claims

1. A biasing circuit in a mixed voltage circuit having an input voltage and an output voltage isolated by a pass gate, said biasing circuit configured for selecting a bulk node biasing voltage for said pass gate from among said input voltage and said output voltage and comprising:

a first switch having a first switch terminal for coupling to said input voltage and a second switch terminal for coupling to a bulk node of said pass gate, said first switch further including a control terminal for coupling to said output voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said first switch; and

a second switch having a first switch terminal for coupling to said bulk node of said pass gate and a second switch terminal for coupling to said output voltage, said second switch further including a control terminal for coupling to said input voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said second switch.

2. The biasing circuit, as recited in claim 1, wherein said first switch terminal of said first switch is coupled to a voltage booster of a charge pump for generating said input voltage.

3. The biasing circuit, as recited in claim 1, wherein said biasing circuit is an integrated circuit on a common substrate.

4. The biasing circuit, as recited in claim 3, wherein said integrated circuit is a memory device.

5. The biasing circuit, as recited in claim 1, wherein said first and second switches include first and second transistors.

6. The biasing circuit, as recited in claim 5, wherein said first and second transistors are metal-oxide (MOS) transistors.

7. The biasing circuit, as recited in claim 6, wherein said first and second transistors are p-channel transistors.

8. The biasing circuit, as recited in claim 1, so configured that when said input voltage and said output voltage are less than a threshold voltage of either of said first switch and said second switch, neither of said first switch and said second switch enables conduction to allow said bulk node of said pass gate to float.

9. A circuit to isolate an input voltage and an output voltage and transfer charge from a charge pumping voltage booster to an output voltage load, said circuit comprising:

a pass gate including an input terminal, an output terminal, a gate control terminal and a bulk node;

a biasing circuit for selecting a bulk node biasing voltage for said pass gate from among said input voltage and said output voltage, including;

a first switch having a first switch terminal for coupling to said input voltage and a second switch terminal for coupling to said bulk node of said pass gate, said first switch further including a control terminal for coupling to said output voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said first switch; and

a second switch having a first switch terminal for coupling to said bulk node of said pass gate and a second switch terminal for coupling to said output voltage, said second switch further including a control terminal for coupling to said input voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said second switch.

10. The circuit, as recited in claim 9, wherein said first switch terminal of said first switch is coupled to a voltage booster of a charge pump for generating said input voltage.

11. The circuit, as recited in claim 9, wherein said biasing circuit is an integrated circuit on a common substrate.

12. The circuit, as recited in claim 11, wherein said integrated circuit is a memory device.

13. The circuit, as recited in claim 9, wherein said first and second switches of said biasing circuit comprise first and second transistors.

14. The circuit, as recited in claim 13, wherein said first and second transistors are metal-oxide (MOS) transistors.

15. A charge pump for converting an input voltage to an output voltage of a different magnitude or polarity, comprising:

a voltage booster for coupling to said input voltage for switching stored charge to said different magnitude or polarity from said input voltage;

a pass gate for providing isolation between said input voltage and said output voltage, said pass gate coupled to said voltage booster at an input terminal of said pass gate, said pass gate further including an output terminal, a gate terminal, and a bulk node; and

a biasing circuit for selecting a bulk node biasing voltage for said pass gate from among said input voltage and said output voltage, including;

a first switch having a first switch terminal for coupling to said input voltage and a second switch terminal for coupling to said bulk node of said pass gate, said first switch further including a control terminal for coupling to said output voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said first switch; and

a second switch having a first switch terminal for coupling to said bulk node of said pass gate and a second switch terminal for coupling to said output voltage, said second switch further including a control terminal for coupling to said input voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said second switch.

16. A charge pump, comprising:

a voltage booster responsive to an input voltage for switching stored charge from said input voltage to a boosted voltage of a different magnitude or polarity from said input voltage;

a pass gate coupled at an input terminal to receive said boosted voltage of said voltage booster and to isolate and transfer said boosted voltage to an output terminal of said pass gate as an output voltage of said charge pump when switched in response to a pass gate control signal at a gate terminal of said pass gate; and

a biasing circuit coupled to said boosted voltage and said output voltage of said charge pump for biasing a bulk node of said pass gate with a potential comprising the greater of a potential of said boosted voltage and a potential of said output voltage.

17. The charge pump, as recited in claim 16, wherein said charge pump is an integrated circuit on a common substrate.

18. The charge pump, as recited in claim 17, wherein said integrated circuit is a memory device.

19. The charge pump, as recited in claim 16, wherein said charge pump is a metal-oxide semiconductor (MOS) integrated circuit.

20. The charge pump, as recited in claim 16, wherein said biasing circuit includes:

a first switch having a first switch terminal for coupling to said input voltage and a second switch terminal for coupling to said bulk node of said pass gate, said first switch further including a control terminal for coupling to said output voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said first switch; and

a second switch having a first switch terminal for coupling to said bulk node of said pass gate and a second switch terminal for coupling to said output voltage, said second switch further including a control terminal for coupling to said input voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said second switch.

21. A charge pump, comprising:

a plurality of voltage boosters responsive to an input voltage for switching stored charge from said input voltage to an individual one of a respective plurality of boosted voltages of a different magnitude or polarity from said input voltage;

a corresponding plurality of pass gates, each respectively coupled to said plurality of voltage boosters to individually receive a respective one of said plurality of boosted voltages and to isolate and transfer said plurality of boosted voltages to an individual corresponding output terminal of said plurality of pass gates as a unified output voltage of said charge pump in response to at least one pass gate control signal coupled to an individually corresponding plurality of pass gate control terminals; and

a corresponding plurality of biasing circuits, each individually coupled to said plurality of boosted voltages and said output voltage of said charge pump for biasing an individually respective plurality of bulk nodes of said plurality of pass gates with a greater potential of either said respective one of said plurality of boosted voltages or said output voltage.

22. An integrated memory device comprising:

an array of memory cells operative with a first voltage and a second voltage different in magnitude or polarity from said first voltage; and

a charge pump coupled to at least a portion of said array of memory cells to generate said second voltage from said first voltage, said charge pump including;

a voltage booster responsive to said first voltage for switching stored charge from said first voltage to a boosted voltage of a different magnitude or polarity from said first voltage;

a pass gate coupled at an input terminal to receive said boosted voltage of said voltage booster and to isolate and transfer said boosted voltage to an output terminal of said pass gate as a second voltage of said charge pump when switched in response to a pass gate control signal at a gate terminal of said pass gate; and

a biasing circuit coupled to said boosted voltage and said second voltage of said charge pump for biasing a bulk node of said pass gate with the greater potential of either said boosted voltage or said second voltage.

23. The integrated memory device, as recited in claim 22, wherein said integrated memory device is of metal-oxide semiconductor (MOS) composition.

24. The integrated memory device, as recited in claim 23, wherein said pass gate and said biasing circuit are comprised of p-channel transistors.

25. The integrated memory device, as recited in claim 22, wherein said biasing circuit is configured for selecting a bulk node biasing voltage for said pass gate from among said boosted voltage and said second voltage, said biasing circuit including:

a first switch having a first switch terminal for coupling to said boosted voltage and a second switch terminal for coupling to said bulk node of said pass gate, said first switch further including a control terminal for coupling to said second voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said first switch; and

a second switch having a first switch terminal for coupling to said bulk node of said pass gate and a second switch terminal for coupling to said second voltage, said second switch further including a control terminal for coupling to said boosted voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said second switch.

26. The integrated memory device, as recited in claim 25, so configured that when said boosted voltage and said second voltage are less than a threshold voltage of either of said first switch or said second switch, neither of said first switch nor said second switch enables conduction to allow said bulk node of said pass gate to float.

27. A computer system, comprising:

a processor; and

a memory system operably coupled to said processor including;

an array of memory cells operative with a first voltage and a second voltage different in magnitude or polarity from said first voltage; and

a charge pump coupled to at least a portion of said array of memory cells to generate said second voltage from said first voltage, said charge pump including a biasing circuit for biasing a bulk node of a pass gate used to isolate and transfer charge from said first voltage to form said second voltage, said biasing circuit configured for biasing a bulk node of said pass gate with the greater of a potential at an input terminal and a potential at an output terminal of said pass gate.

28. The computer system, as recited in claim 27, wherein said charge pump comprises:

a voltage booster responsive to said first voltage for switching stored charge from said first voltage to a boosted voltage of a different magnitude or polarity from said first voltage;

wherein said pass gate is coupled at an input terminal to receive said boosted voltage of said voltage booster and to isolate and transfer said boosted voltage to an output terminal of said pass gate as said second voltage of said charge pump when switched in response to a pass gate control signal at a gate terminal of said pass gate; and

wherein the biasing circuit is coupled to said boosted voltage and said second voltage of said charge pump for biasing said bulk node of said pass gate with the greater of a potential of said boosted voltage and a potential of said second voltage.

29. The computer system, as recited in claim 28, wherein said biasing circuit is configured for selecting a bulk node biasing voltage for said pass gate from among said boosted voltage and said second voltage, including:

a first switch having a first switch terminal for coupling to said boosted voltage and a second switch terminal for coupling to said bulk node of said pass gate, said first switch further including a control terminal for coupling to said second voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said first switch; and

a second switch having a first switch terminal for coupling to said bulk node of said pass gate and a second switch terminal for coupling to said second voltage, said second switch further including a control terminal for coupling to said switched voltage, said control terminal responsive to an applied voltage to enable conduction between said first switch terminal and said second switch terminal of said second switch.

30. An integrated circuit comprising:

a circuit operative with a first voltage and a second voltage different in magnitude or polarity from said first voltage; and

a charge pump coupled to at least a portion of said circuit to generate said second voltage from said first voltage, said charge pump including;

a voltage booster responsive to said first voltage for switching stored charge from said first voltage to a boosted voltage of a different magnitude or polarity from said first voltage;

a pass gate coupled at an input terminal to receive said boosted voltage of said voltage booster and to isolate and transfer said boosted voltage to an output terminal of said pass gate as a second voltage of said charge pump when switched in response to a pass gate control signal at a gate terminal of said pass gate; and

a biasing circuit coupled to said boosted voltage and said second voltage of said charge pump for biasing a bulk node of said pass gate with a greater of a potential of said boosted voltage and a potential of said second voltage.

31. An integrated circuit, comprising:

a first circuit portion operative on a first voltage;

a second circuit portion operative on a second voltage; and

a charge pump operably coupled to said first circuit portion and said second circuit portion, said charge pump configured for generating said second voltage from said first voltage, including;

a voltage booster responsive to said first voltage for switching stored charge from said first voltage to a boosted voltage of a different magnitude or polarity from said first voltage;

a pass gate coupled at an input terminal to receive said boosted voltage of said voltage booster and to isolate and transfer said boosted voltage to an output terminal of said pass gate as a second voltage of said charge pump when switched in response to a pass gate control signal at a gate terminal of said pass gate; and

a biasing circuit coupled to said boosted voltage and said second voltage of said charge pump for biasing a bulk node of said pass gate with a greater of a potential of said boosted voltage and a potential of said second voltage.

32. A method of biasing a bulk node of a pass gate in a charge pump, the method comprising:

monitoring first and second voltages at input and output terminals, respectively, of said pass gate;

selecting one of said first and second voltages having a greater potential; and

coupling said one of said first and second voltages having a greater potential to said bulk node of said pass gate of said charge pump.

33. The method as recited in claim 32, wherein selecting comprises:

coupling a first switch having a first switch terminal to said first voltage, coupling a second switch terminal to said bulk node of said pass gate, and coupling a control terminal to said second voltage; and

coupling a second switch having a first switch terminal to said bulk node of said pass gate, coupling a second switch terminal to said second voltage, and coupling a control terminal to said first voltage.

34. The method, as recited in claim 33, wherein coupling comprises:

activating one of said first and second switches when said first and second voltages vary by more than a threshold voltage of one of said first and second switches.

35. The method, as recited in claim 34, wherein coupling further comprises:

floating said bulk node when said first and second voltages differ by less than said threshold voltage.