Providing different clock frequencies for different interfaces of a device

• US 20040071159A1
• Filed: 10/14/2002
• Published: 04/15/2004
• Est. Priority Date: 10/14/2002
• Status: Active Grant

• Current Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Original Assignee: Lexmark International Incorporated (Ninestar Corporation)
• Inventors: Norris, Duane E., Moore, Jimmy D. Jr., Henry, Darrel L., Douglas, John W., Gardiner, Samuel W.
• Granted Patent: US 7,278,047 B2
• Time in Patent Office: Days
• US Class Current: 370/465
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A method for operating a device (such as a printer) having a first interface (such as USB interface) connectable to a first computer and a second interface (such as an Ethernet interface) connectable to a second computer. A phase lock loop (PLL) circuit is obtained which is driven by a clock source, which is adapted for switching between operating at the first and second clock frequencies, and which is operatively connected to the first and second interfaces to provide a clock signal to the first and second interfaces. The PLL circuit is operated at the first clock frequency when the first interface is active and is operated at the second clock frequency when the second interface is active. A device includes the first and second interfaces, the PLL circuit, and the clock source.

Claims

1. A method for operating a printer having a Universal Serial Bus (USB) interface connectable to a first computer and having an Ethernet interface connectable to a second computer, wherein the USB interface operates at a USB clock frequency and the Ethernet interface operates at a different Ethernet clock frequency, wherein the printer communicates over only one of the USB and Ethernet interfaces at the same time, and wherein the method comprises the steps of:

a) obtaining a clock source having a set base frequency;

b) obtaining a phase lock loop circuit adapted for switching between operating at the USB and Ethernet clock frequencies when driven by the clock source;

c) driving the phase lock loop circuit with the clock source;

d) operatively connecting the phase lock loop circuit to the USB and Ethernet interfaces to provide a clock signal to the USB and Ethernet interfaces;

e) operating the phase lock loop circuit at the USB clock frequency when the USB interface is active;

f) operating the phase lock loop circuit at the Ethernet clock frequency when the Ethernet interface is active;

g) determining that the USB interface is active when power (VBUS) supplied over the USB interface by the first computer to the printer is present and when a link between the second computer and the printer is not established on the Ethernet interface physical layer (PHY) that controls the signaling rate on the network; and

h) determining that the Ethernet interface is active when a link is established between the second computer and the printer on the Ethernet interface PHY before VBUS is present.

2. The method of claim 1, including the step of operatively disconnecting the Ethernet interface from the phase lock loop circuit when the USB interface is active.

3. The method of claim 2, wherein the Ethernet interface is operatively disconnected from the phase lock loop circuit by holding the Ethernet interface PHY in reset.

4. The method of claim 3, wherein the Ethernet interface PHY has a logic-low reset pin, wherein the USB interface includes a pull-up pin which controls a pull-up resistor on a data line on the USB interface, wherein the USB interface drives the pull-up pin high if VBUS is present and drives the pull-up pin low if VBUS is not present, and wherein the pull-up pin is connected through an inverting transistor to the reset pin for the reset pin to hold the Ethernet interface PHY in reset when the USB interface is active.

5. A method for operating a device having a Universal Serial Bus (USB) interface connectable to a first computer and having an Ethernet interface connectable to a second computer, wherein the USB interface operates at a USB clock frequency and the Ethernet interface operates at a different Ethernet clock frequency, wherein the device communicates over only one of the USB and Ethernet interfaces at the same time, and wherein the method comprises the steps of:

a) obtaining a clock source having a set base frequency;

b) obtaining a phase lock loop circuit adapted for switching between operating at the USB and Ethernet clock frequencies when driven by the clock source;

c) driving the phase lock loop circuit with the clock source;

d) operatively connecting the phase lock loop circuit to the USB and Ethernet interfaces to provide a clock signal to the USB and Ethernet interfaces;

e) operating the phase lock loop circuit at the USB clock frequency when the USB interface is active; and

f) operating the phase lock loop circuit at the Ethernet clock frequency when the Ethernet interface is active.

6. The method of claim 5, wherein the device is a printer.

7. The method of claim 5, wherein the USB clock frequency is substantially 48 megahertz (MHz) and the Ethernet clock frequency is substantially 25 MHz.

8. The method of claim 7, wherein the clock source is one of a crystal and a resonator, and wherein the set base frequency of the clock source is one of 24 and 48 MHz.

9. The method of claim 5, also including the step of determining that the USB interface is active when power (VBUS) supplied over the USB interface by the first computer to the device is present and when a link between the second computer and the device is not established on the Ethernet interface physical layer (PHY) that controls the signaling rate on the network.

10. The method of claim 9, also including the step of determining that the Ethernet interface is active when a link is established between the second computer and the device on the Ethernet interface PHY before VBUS is present.

11. The method of claim 5, also including the step of determining that the Ethernet interface is active when a link is established between the second computer and the device on the Ethernet interface physical layer (PHY) that controls the signaling rate on the network before power (VBUS) supplied over the USB interface by the first computer to the device is present.

12. The method of claim 5, also including the step of operatively disconnecting the Ethernet interface from the phase lock loop circuit when the USB interface is active.

13. The method of claim 12, wherein the Ethernet interface is operatively disconnected from the phase lock loop circuit by holding the Ethernet interface PHY in reset.

14. The method of claim 13, wherein the Ethernet interface PHY has a logic-low reset pin, wherein the USB interface includes a pull-up pin which controls a pull-up resistor on a data line on the USB interface, wherein the USB interface drives the pull-up pin high if VBUS is present and drives the pull-up pin low if VBUS is not present, and wherein the pull-up pin is connected through an inverting transistor to the reset pin for the reset pin to hold the Ethernet interface PHY in reset when the USB interface is active.

15. A method for operating a device having a first interface connectable to a first computer and having a second interface connectable to a second computer, wherein the first interface operates at a first clock frequency and the second interface operates at a different second clock frequency, wherein the device communicates over only one of the first and second interfaces at the same time, and wherein the method comprises the steps of:

a) obtaining a clock source having a set base frequency;

b) obtaining a phase lock loop circuit adapted for switching between operating at the first and second clock frequencies when driven by the clock source;

c) driving the phase lock loop circuit with the clock source;

d) operatively connecting the phase lock loop circuit to the first and second interfaces to provide a clock signal to the first and second interfaces;

e) operating the phase lock loop circuit at the first clock frequency when the first interface is active; and

f) operating the phase lock loop circuit at the second clock frequency when the second interface is active.

16. The method of claim 15, wherein the device is a printer.

17. The method of claim 15, wherein the first interface is a non-network interface and the second interface is a network interface;

18. The method of claim 17, wherein the first interface is a Universal Serial Bus (USB) interface and the second interface is an Ethernet interface.

19. The method of claim 18, wherein the device is a printer.

20. A device comprising:

a) a first interface which is connectable to a first computer and which operates at a first clock frequency;

b) a second interface which is connectable to a second computer and which operates at a different second clock frequency;

c) a clock source having a set base frequency; and

d) a phase lock loop circuit which is driven by the clock source, which is adapted for switching between operating at the first and second clock frequencies, and