Precision timing generation

• US 20040071249A1
• Filed: 10/10/2002
• Published: 04/15/2004
• Est. Priority Date: 10/10/2002
• Status: Active Grant

• Current Assignee: OL Security LLC (Intellectual Ventures LLC)
• Original Assignee: Bitzmo, Inc.
• Inventors: Schell, Stephan
• Granted Patent: US 7,221,724 B2
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03K 5/15013 with more than two outputs
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H03L 7/0998 using phase interpolation
• CPC Class Codes: H04B 1/7183 Synchronisation

Abstract

A precision timing generator and an associate method provide a precise clock signal based on a reference clock signal. Using the reference clock signal in a phase locked loop or delay locked loop, a number of clock signals of equal frequency are generated separated consecutively by a known phase. Two of these clock signals of consecutive phases are selected for interpolation for higher precision according to predetermined weights. The resulting interpolated clock signal has a phase offset that is intermediate between the selected clock signals in proportion to the predetermined weights. In one implementation, a second interpolated clock signal is created by selecting and weighting a second group of clock signals using independent selection and weights. The two interpolated clock signals are then combined by logic operations to provide a precise clock signal of predetermined duty cycle and phase.

Claims

1. A precision timing generator, comprising:

a reference clock signal;

a clock generator generating from the reference clock signal a plurality of clock signals of equal frequency, each clock signal being offset from another one of the clock by a predetermined phase;

a first selector circuit selecting a first group of two clock signals, the selected clock signals being offset from each other by the predetermined phase; and

a first interpolator circuit receiving the first group of selected clock signals and associating with each clock signal a predetermined weight, and providing a first resulting clock signal that is offset from each of the selected clock signal by less than the predetermined phase and in proportional to the predetermined weights.

2. A precision timing generator as in claim 1, wherein the clock generator comprises a delay locked loop.

3. A precision timing generator as in claim 1, wherein the predetermined weights are expressed as binary fractions summing to a binary ‘

1’

.

4. A precision timing generator as in claim 1, wherein the first interpolator comprises low pass filters that filter the selected clock signals.

5. A precision timing generator as in claim 4, wherein the first interpolator further comprises variable gain amplifiers that amplify the filtered selected clock signals according to the associated weights.

6. A precision timing generator as in claim 5, wherein the first interpolator further comprises a summer that sums the amplified filtered selected clock signals to provide the resulting clock signal.

7. A precision timing generator as in claim 1, further comprising:

a second selector circuit selecting a second group of two clock signals, the selected clock signals being offset from each other by the predetermined phase;

a second interpolator circuit receiving the second group of selected clock signals and associating with each clock signal a predetermined weight, and providing a second resulting clock signal that is offset from each of the selected clock signal by less than the predetermined phase and in proportional to the predetermined weights; and

a logic gate applying a logic operation on the first resulting clock signal and the second resulting clock signal to provide a precision clock signal.

8. A precision clock generator as in claim 1, further comprising a ultra-wide bandwidth pulse generator providing pulses in accordance with the first resulting clock signal.

9. A method for precision timing generation, comprising:

providing a reference clock signal;

generating from the reference clock signal a plurality of clock signals of equal frequency, each clock signal being offset from another one of the clock by a predetermined phase;

selecting a first group of two clock signals, the selected clock signals being offset from each other by the predetermined phase; and

associating with each clock signal a predetermined weight and interpolating the selected clock signals to provide a first resulting clock signal that is offset from each of the selected clock signal by less than the predetermined phase and in proportional to the predetermined weights.

10. A method for precision timing generation as in claim 9, wherein the clock signals are generated using a delay locked loop.

11. A method for precision timing generation as in claim 9, wherein the predetermined weights are expressed as binary fractions summing to a binary ‘

1’

.

12. A method for precision timing generation as in claim 9, wherein the interpolating comprises low pass filtering the selected clock signals.

13. A method for precision timing generation as in claim 12, wherein the interpolating further comprises using variable gain amplifiers to amplify the filtered selected clock signals according to the associated weights.

14. A method for precision timing generation as in claim 13, wherein the interpolating further comprises summing the amplified filtered selected clock signals to provide the resulting clock signal.

15. A method for precision timing generation as in claim 9, further comprising:

selecting a second group of two clock signals, the selected clock signals being offset from each other by the predetermined phase;

associating with each clock signal of the second group of selected clock signals a predetermined weight, and interpolating the second group of selected clock signals to provide a second resulting clock signal that is offset from each of the selected clock signal by less than the predetermined phase and in proportional to the predetermined weights; and

applying a logic operation on the first resulting clock signal and the second resulting clock signal to provide a precision clock signal.

16. A method for precision clock generation as in claim 9, further comprising generating ultra-wide bandwidth pulses in accordance with the first resulting clock signal.