Clock offset compensator

• US 20040071251A1
• Filed: 10/09/2002
• Published: 04/15/2004
• Est. Priority Date: 10/09/2002
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Sutioso, Henri, Wu, Lei
• Granted Patent: US 7,263,153 B2
• Time in Patent Office: Days
• US Class Current: 375/373
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A device communicates with a host and includes a transmitter, a receiver and a clock generator that generates a local clock frequency. A clock recovery circuit communicates with the receiver and recovers a host clock frequency from data received from the host by the receiver. A frequency offset circuit communicates with the clock recovery circuit and the clock generator and generates a frequency offset based on the clock frequency and the recovered host clock frequency. A frequency compensator compensates a frequency of the transmitter using the frequency offset. The host and the device may communicate using a serial ATA standard. Frequency compensation can be performed during spread spectrum operation.

Claims

1. A device that communicates with a host, comprising:

a transmitter;

a receiver;

a clock generator that generates a local clock frequency;

a clock recovery circuit that communicates with said receiver and that recovers a host clock frequency from data received from said host by said receiver;

a frequency offset circuit that communicates with said clock recovery circuit and said clock generator and that generates a frequency offset based on said clock frequency and said recovered host clock frequency; and

a frequency compensator that compensates a frequency of said transmitter using said frequency offset.

2. The device of claim 1 wherein said frequency compensator includes a low pass filter that communicates with said frequency offset circuit.

3. The device of claim 2 wherein said frequency compensator includes an accumulator that communicates with said low pass filter and that generates a phase offset.

4. The device of claim 3 wherein said frequency compensator includes an interpolator that receives a local phase from said clock generator and said phase offset from said accumulator and wherein said interpolator outputs a compensated clock signal to said transmitter.

5. The device of claim 1 wherein said clock generator includes a phase-locked loop circuit that includes:

a reference frequency generator;

a phase detector that communicates with said reference frequency generator;

a low pass filter that communicates with said phase detector; and

a voltage controlled oscillator that communicates with said low pass filter.

6. The device of claim 5 wherein said reference frequency generator includes at least one of a crystal resonator and a ceramic resonator.

7. The device of claim 5 further comprising a 1/N divider having an input that communicates with said voltage controlled oscillator and an output that communicates with said phase detector, and a 1/M divider having an input that communicates with said reference frequency generator and an output that communicates with said phase detector, wherein N and M are adjusted to create a spread spectrum modulation signal for spread spectrum operation.

8. The device of claim 7 further comprising an interpolator that communicates with an output of said voltage controlled oscillator and an input of said 1/N divider.

9. The device of claim 4 further comprising:

a summer having a first input that communicates with an output of said lowpass filter and an output that communicates with an input of said accumulator; and

a frequency modulation generator that communicates with a second input of said summer and that selectively generates a spread spectrum modulation signal when spread spectrum operation is enabled and a constant signal when spread spectrum operation is disabled.

10. The device of claim 1 wherein said host and said device communicate using a serial ATA standard.

11. The device of claim 1 wherein said host is a disk controller and said device is a disk drive.

12. A communication system including:

a host including a host transmitter, a host receiver, and a host clock generator that generates a host clock frequency; and

a device that communicates with said host using a serial ATA standard and that includes a device transmitter, a device receiver, a device clock generator that generates a local clock frequency, a clock recovery circuit that recovers said host clock frequency from data received from said host by said device receiver, a frequency offset circuit that generates a frequency offset based on said local clock frequency and said recovered host clock frequency, and a frequency compensator that compensates a frequency of said device transmitter using said frequency offset.

13. The communication system of claim 12 wherein said frequency compensator includes a low pass filter that communicates with said frequency offset circuit.

14. The communication system of claim 13 wherein said frequency compensator includes an accumulator that communicates with said low pass filter and that generates a phase offset.

15. The communication system of claim 14 wherein said frequency compensator includes an interpolator that receives a local phase from said device clock generator and said phase offset from said accumulator.

16. The communication system of claim 12 wherein said device clock generator includes a phase-locked loop circuit that includes:

a reference frequency generator;

a phase detector that communicates with said reference frequency generator;

a low pass filter that communicates with said phase detector; and

a voltage controlled oscillator that communicates with said low pass filter.

17. The communication system of claim 16 wherein said reference frequency generator includes at least one of a crystal resonator and a ceramic resonator.

18. The communication system of claim 16 further comprising a 1/N divider having an input that communicates with said voltage controlled oscillator and an output that communicates with said phase detector, and a 1/M divider having an input that communicates with said reference frequency generator and an output that communicates with said phase detector, wherein N and M are adjusted to create a spread spectrum modulation signal for spread spectrum operation.

19. The communication system of claim 18 further comprising an interpolator that communicates with an output of said voltage controlled oscillator and an input of said 1/N divider.

20. The communication system of claim 15 further comprising:

a summer having a first input that communicates with an output of said lowpass filter and an output that communicates with an input of said accumulator; and

a frequency modulation generator that communicates with a second input of said summer and that selectively generates a spread spectrum modulation signal when spread spectrum operation is enabled and a constant when spread spectrum operation is disabled.

21. The communication system of claim 12 wherein said host is a disk controller and said device is a disk drive.

22. A frequency offset compensator for a device that communicates with a host, comprising:

a clock data recovery and frequency offset calculator that generates a frequency offset;

a frequency modulation generator that generates a spread spectrum modulation signal when spread spectrum operation is enabled; and

a summer that adds said frequency offset and an output of said frequency modulation generator to generate a summed frequency offset;

a conversion circuit that converts said summed frequency offset to a phase offset.

23. The frequency offset compensator of claim 22 wherein said frequency modulation generator outputs a constant when spread spectrum operation is disabled and wherein said summer adds said frequency offset and said constant when said spread spectrum operation is disabled.

24. The frequency offset compensator of claim 22 further comprising:

a device transmitter;

a device clock that generates a local phase; and

an interpolator that has a first input that receives said local phase, a second input that receives an output of said summer, and an output that communicates with a transmitter of said device.

25. A device that communicates with a host, comprising:

transmitting means for transmitting data to said host;

receiving means for receiving data from said host;

clock generating means for generating a local clock frequency;

clock recovery means for recovering a host clock frequency from data received from said host by said receiving means;

frequency offset means for generating a frequency offset based on said clock frequency and said recovered host clock frequency; and

frequency compensating means for compensating a frequency of said transmitting means using said frequency offset.

26. The device of claim 25 wherein said frequency compensating means includes filtering means for filtering an output of said frequency offset means.

27. The device of claim 26 wherein said frequency compensating means further includes accumulating means that communicates with said filtering means for generating a phase offset.

28. The device of claim 27 wherein said frequency compensating means further includes interpolating means that receives a local phase from said clock generating means and said phase offset from said accumulating means for generating a compensated clock signal for said transmitting means.

29. The device of claim 25 wherein said clock generating means includes a phase-locked loop circuit that includes:

generating means for generating a reference frequency;

detecting means for detecting a phase of said reference frequency;

filtering means for filtering said phase output by said detecting means; and

a voltage controlled oscillator that communicates with said filtering means.

30. The device of claim 29 wherein said generating means includes at least one of a crystal resonator and a ceramic resonator.

31. The device of claim 29 further comprising:

first dividing means having an input that communicates with said voltage controlled oscillator and an output that communicates with said detecting means for dividing an output of said voltage controlled oscillator by N; and

second dividing means having an input that communicates with said generating means and an output that communicates with said detecting means for dividing said reference frequency by M, wherein N and M are adjusted to create a spread spectrum modulation signal for spread spectrum operation.

32. The device of claim 31 further comprising:

frequency modulation generating means for generating a spread spectrum modulation signal;

accumulating means that communicates with an output of said frequency modulation generating means for generating a phase from said spread spectrum modulation signal; and

interpolating means for communicating with an output of said voltage controlled oscillator and said accumulating means and an input of said first dividing means.

33. The device of claim 28 further comprising:

frequency modulation generating means for selectively generating a spread spectrum modulation signal when spread spectrum operation is enabled and a constant signal when spread spectrum operation is disabled; and

summing means for summing an output of said filtering means and said frequency modulation generating means and having an output that communicates with an input of said accumulating means.

34. The device of claim 25 wherein said host and said device communicate using a serial ATA standard.

35. The device of claim 25 wherein said host is a disk controller and said device is a disk drive.

36. A communication system including:

a host including host transmitting means for transmitting data, host receiving means for receiving data, and host clock generating means for generating a host clock frequency; and

a device that communicates with said host using a serial ATA standard and that includes device transmitting means for transmitting data, device receiving means for receiving data, device clock generating means for generating a local clock frequency, clock recovery means for recovering said host clock frequency from data received from said host by said device receiving means, frequency offset means for generating a frequency offset based on said local clock frequency and said recovered host clock frequency, and frequency compensating means for compensating a frequency of said device transmitting means based on said frequency offset.

37. The communication system of claim 36 wherein said frequency compensating means includes filtering means for filtering said frequency offset.

38. The communication system of claim 37 wherein said frequency compensating means further includes accumulating means that communicates with said filtering means for generating a phase offset.

39. The communication system of claim 38 wherein said frequency compensating means includes interpolating means for receiving a local phase from said device clock generating means and said phase offset from said accumulating means.

40. The communication system of claim 36 wherein said device clock generator includes a phase-locked loop circuit that includes:

generating means for generating a reference frequency;

detecting means for detecting a phase of said reference frequency;

filtering means for filtering said phase; and

a voltage controlled oscillator that communicates with said filtering means.

41. The communication system of claim 40 wherein said generating means includes at least one of a crystal resonator and a ceramic resonator.

42. The communication system of claim 40 further comprising:

first dividing means having an input that communicates with said voltage controlled oscillator and an output that communicates with said detecting means for dividing an output of said voltage controlled oscillator by N; and

second dividing means having an input that communicates with said generating means and an output that communicates with said detecting means for dividing said reference frequency by M, wherein N and M are adjusted to create a spread spectrum modulation signal for spread spectrum operation.

43. The communication system of claim 42 further comprising interpolating means for communicating with an output of said voltage controlled oscillator and an input of said first dividing means.

44. The communication system of claim 39 further comprising:

frequency modulation generating means for selectively generating a spread spectrum modulation signal when spread spectrum operation is enabled and a constant when spread spectrum operation is disabled; and

summing means for summing an output of said filtering means and said frequency modulation generating means and having an output that communicates with an input of said accumulating means.

45. The communication system of claim 36 wherein said host is a disk controller and said device is a disk drive.

46. A frequency offset compensator for a device that communicates with a host, comprising:

offset calculating means for generating a frequency offset;

frequency modulation generating means for generating a spread spectrum modulation signal when spread spectrum operation is enabled;

summing means for generating a summed frequency offset by summing said frequency offset and said spread spectrum modulation signal; and

conversion means for converting said summed frequency offset to a phase offset.

47. The frequency offset compensator of claim 46 wherein said frequency modulation generating means outputs a constant when spread spectrum operation is disabled and wherein said summing means adds said frequency offset and said constant when said spread spectrum operation is disabled.

48. The frequency offset compensator of claim 46 further comprising:

device transmitting means for transmitting data;

device clocking means for generating a local phase; and

interpolating means for receiving said local phase and said phase offset and for compensating a clock of said device transmitting means.

49. A method for operating a device that communicates with a host, comprising:

transmitting data to said host;

receiving data from said host;

generating a local clock frequency;

recovering a host clock frequency from data received from said host;

generating a frequency offset based on said clock frequency and said recovered host clock frequency; and

compensating a transmitting frequency using said frequency offset.

50. The method of claim 49 further comprising low pass filtering said frequency offset.

51. The method of claim 50 further comprising generating a phase offset from said filtered frequency offset.

52. The method of claim 51 further comprising generating a compensated clock signal for said transmitted data based on a local phase and said phase offset.

53. The method of claim 49 wherein said step of generating said local clock includes using a phase-locked loop.

54. The method of claim 53 wherein a reference frequency of said phase-locked loop is generated by at least one of a crystal resonator and a ceramic resonator.

55. A method for providing frequency offset compensation for a device that communicates with a host, comprising:

generating a frequency offset;

generating a spread spectrum modulation signal when spread spectrum operation is enabled;

summing said frequency offset and said spread spectrum modulation signal to generate a summed frequency offset; and

converting said summed frequency offset to a phase offset.

56. The method of claim 55 further comprising:

generating a constant signal when spread spectrum operation is disabled; and

summing said frequency offset and said constant when said spread spectrum operation is disabled to generate said summed frequency offset.

57. The method of claim 55 further comprising:

transmitting data from said device;

generating a local phase; and

compensating a transmitter clock based on said local phase and said phase offset.