Chip alignment and placement apparatus for integrated circuit, mems, photonic or other devices

• US 20040072385A1
• Filed: 10/15/2002
• Published: 04/15/2004
• Est. Priority Date: 10/15/2002
• Status: Abandoned Application

• Current Assignee: Meadwestvaco (WestRock Company)
• Original Assignee: Meadwestvaco (WestRock Company)
• Inventors: Collins, Richard A., Bryden, Michelle D., Bauer, Donald G., Spedden, Richard H.
• Application Number:
  US10/269,326
• Publication Number:
  US 20040072385A1
• Time in Patent Office: Days
• US Class Current: 438/68
• CPC Class Codes: H01L 21/67132 Apparatus for placing on an insulating substrate, e.g. tape
• CPC Class Codes: H01L 21/67144 Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/75 Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

Devices for manipulating, receiving and dispensing diced semiconductor materials, in which the semiconductor material is diced to provide partially connected dice in linear aggregations.

Claims

1. A method of processing semiconductor chips for integrated circuit, MEMS or photonic device manufacture comprising:

at least partly severing a wafer of semiconductor material in at least one dimension to provide at least one parting line;

completely severing the wafer in a dimension perpendicular to the at least one parting line to form one or more linear chip aggregations composed of partially joined individual chips, each linear chip aggregation being separated by one or more severed edges of the individual chips;

aligning the one or more linear chip aggregations with reception sites on a substrate;

dispensing individual chips from the one or more linear chip aggregations onto the reception sites by severing a single chip from each linear chip aggregation and contacting it with the surface of the substrate while simultaneously preserving its linear orientation and controlling its alignment on the surface of the substrate.

2. The method of claim 1, in which the step of at least partly severing the wafer is performed by sawing through less than the entire thickness of the wafer.

3. The method of claim 2 in which the semiconductor wafer is backed by an adhesive material and the step of at least partly severing the wafer does not sever the adhesive material.

4. The method of claim 1 in which the dispensing of individual chips includes extending a single chip over a reception site and perpendicularly applying pressure from a tamping means to the bottom face of the chip to sever it from the linear chip aggregation and deposit it on the reception site.

5. The method of claim 1 in which the dispensing of individual chips includes extending a single chip over a reception site and severing the single chip from the linear chip aggregation by applying force from a sliding member.

6. The method of claim 1 in which the dispensing of individual chips includes extending a single chip over a reception site and dispensing the single chip from the linear chip aggregation by applying force from a device having a rotating member.

7. The method of claim 1 in which the dispensing of individual chips includes extending a single chip over a reception site and severing the single chip from the linear chip aggregation using a shutter device.

8. The method of claim 1 in which the dispensing of individual chips includes providing within the dispensing device a tape material to assist in fastening the chip to the substrate.

9. The method of claim 8 in which the tape material comprises conductive side areas for bonding to electrically active areas of the substrate, a non-conductive area between the conductive side areas, and an anisotropic conductive region for bonding to electrically active areas of the chip.

10. The method of claim 1 wherein the method of dispensing individual chips is synchronized using a sensor to detect the position of the target.

11. A stapler apparatus for dispensing diced semiconductor materials on a substrate, comprising:

one or more chambers for receiving and holding one or more linear chip aggregations; and

a dispensing device that releases individual chips from the one or more linear chip aggregations held within said chambers onto reception sites on a substrate.

12. The stapler apparatus of claim 11 where the dispensing device further includes a shutter means.

13. The apparatus of claim 11 where the dispensing device further includes a slidable member for separating individual chips from the one or more linear chip aggregations.

14. The apparatus of claim 11 where the dispensing device further includes a rotatable member for separating individual chips from the one or more linear chip aggregations.

15. The apparatus of claim 11 further comprising one or more first tamping means for loading the linear chip aggregations into the chambers.

16. The apparatus of claim 11 further comprising one or more second tamping means for dispensing chips from the dispensing device.

17. A rotary magazine for receiving and dispensing linear aggregations of diced semiconductor chips comprising at least one sleeve surrounding a core cylinder;

and a series of chambers on the interior or exterior of the at least one sleeve, each chamber accommodating one or a series of linear aggregations of semiconductor chips therein.

18. The rotary magazine of claim 17 further including one or more ports for vacuum or pressure application to the chambers.