Method for monitoring end of life for battery

• US 20040073264A1
• Filed: 10/07/2003
• Published: 04/15/2004
• Est. Priority Date: 09/15/1997
• Status: Active Grant

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Lyden, Michael J.
• Granted Patent: US 7,515,962 B2
• Time in Patent Office: Days
• US Class Current: 607/7
• CPC Class Codes: A61N 1/3708 for power depletion
• CPC Class Codes: G01R 31/3647 for determining the ability of a battery to perform a critical function, e.g. cranking
• CPC Class Codes: G01R 31/367 Software therefor, e.g. for battery testing using modelling or look-up tables
• CPC Class Codes: G01R 31/392 Determining battery ageing or deterioration, e.g. state of health
• CPC Class Codes: H02J 2310/23 The load being a medical device, a medical implant, or a life supporting device
• CPC Class Codes: H02J 7/0048 Detection of remaining charge capacity or state of charge [SOC]
• CPC Class Codes: H02J 7/005 Detection of state of health [SOH]

Abstract

A system is described which has a battery, a device which is powered by the battery in an episodic manner, and a charge storage capacitor. The system has attached to the charge storage capacitor a device or devices capable of: reading the rate of charge storage; or measuring both time and charge stored or added to the charge storage capacitor so that a rate of charge storage may be calculated. The estimated replacement time for the battery, particularly for a lithium battery in a pacing device, is easily estimated. Also described herein is a process for estimating a level of energy depletion in the system. The process comprises: finding a relatively quiescent period in powering of the device in the episodic manner; determining a rate of charging in the storage capacitor during the quiescent period; and correlating the rate of charging in the storage capacitor to a value of internal impedance in the battery through a comparison with known relationships for the battery and rate of charging to determine a value for the internal impedance of the battery.

Claims

1. A device, comprising:

a charge storage capacitor;

circuitry connected to the charge storage capacitor, the circuitry including a battery terminal to connect to a battery for powering the circuitry in an episodic manner, the circuitry including;

means to discharge the storage capacitor to a discharge voltage reference;

means to charge the storage capacitor from the discharge voltage reference to a charged voltage reference;

means to measure a charge time for the storage capacitor to determine the rate of charging from an initial voltage level that is larger than the discharge voltage reference to a final voltage level;

means to determine a value for an internal impedance of the battery based on the rate of charging; and

means to estimate the level of power depletion for the battery using the value for the internal impedance of the battery.

2. The device of claim 1, wherein the charged voltage level is the final voltage level.

3. The device of claim 1, wherein the circuitry includes:

a memory;

means to load the memory with a pacing voltage amplitude value to function as the charged voltage reference;

means to load the memory with an initial value to function as the initial voltage level; and

means to load the memory with a discharge value to function as the discharged voltage level.

4. The device of claim 1, further comprising:

means to compare a voltage across the storage capacitor (V_CS) to the discharge voltage reference while discharging the storage capacitor so as to discharge the storage capacitor to the discharge voltage reference;

means to compare V_CS to the initial level while charging the storage capacitor, and to initiate the measuring of the charge time for the storage capacitor when V_CS reaches the initial voltage level; and

means to compare V_CS to the charged voltage reference while charging the storage capacitor so as to charge the storage capacitor to the charged voltage reference, and ending the measuring of the charge time for the storage capacitor when V_CS reaches the charged voltage reference.

5. The device of claim 1, wherein the system includes a pacing system, the pacing system including means to apply a pace using energy from the storage capacitor.

6. The device of claim 1, wherein the system includes a pacing system, the pacing system including a second capacitor for use to apply a pace using energy from the storage capacitor.

7. The device of claim 1, wherein the battery has an internal impedance characteristic curve which is initially substantially linear as a function of energy depletion, but which asymptotically approaches an energy production limit and increasing internal impedance.

8. The device of claim 7, wherein the internal impedance characteristic curve includes an internal AC impedance characteristic curve.

9. A pacemaker, including:

a battery power terminal for a pacemaker battery;

a capacitor electrically connected to the battery power terminal;

pacemaker control circuitry electrically connected to the battery power terminal and the capacitor for controlling current flow from the battery power terminal to the capacitor to charge the capacitor and to discharge the capacitor to a discharge voltage level (Vd) before beginning a time charge measurement; and

charge time measurement (CTM) control circuitry electrically connected to the pacemaker control circuitry and adapted to;

access a predetermined set of charge time measurement set-up parameters and a predetermined elective replacement time (ERT) charge time limit associated with an AC impedance target for the battery;

determine a rate of charge storage in the capacitor using the predetermined set of charge time measurement set-up parameters; and

declare an ERT using the determined rate of charge storage in the capacitor and the ERT charge time limit,

wherein the predetermined set of charge time measurement set-up parameters to be accessed by the CTM control circuitry include;

a final voltage (VF) to end the charge time measurement for determining the rate of charge storage in the capacitor; and

an initial reference voltage (VI) to begin the charge time measurement for determining the rate of charge storage in the capacitor, VI being greater than Vd.

10. The pacemaker of claim 9, wherein the pacemaker control circuitry includes comparison circuitry for comparing a battery terminal voltage (Vbatt) to a brownout voltage limit (Vstop), and for comparing a capacitor voltage (Vcs) to one of the predetermined set of charge time measurement set-up parameters.

11. The pacemaker of claim 10, wherein the pacemaker control circuitry further includes a switched capacitor power supply operably connected to the battery power terminal and the capacitor for charging the capacitor, wherein an output of the comparison circuitry is electrically connected to the switched capacitor power supply to control current flow from the battery power terminal to the capacitor.

12. The pacemaker of claim 9, wherein the pacemaker control circuitry controls current flow to the capacitor to increase a capacitor voltage (V_cs) approximately linearly from VI to VF during the time measurement for determining the rate of charge storage in the capacitor.

13. The pacemaker of claim 9, wherein:

the CTM control circuitry includes a multiplexer for selecting one of VF and VI to be compared to a capacitor voltage level (V_sc) within the pacemaker control circuitry; and

the CTM control circuitry is adapted to select VI to be compared to Vsc to begin a time charge measurement and VF to be compared to Vsc to end the time charge measurement.

14. The pacemaker of claim 9, wherein the CTM control circuitry includes a time charge counter for measuring a time in which a relatively constant current charges the capacitor from VI to VF.

15. The pacemaker of claim 9, wherein the pacemaker control circuitry includes a sensing and pacing control block adapted for selecting VI.

16. The pacemaker of claim 9, wherein the CTM control circuitry includes a multiplexer for selecting one of the VF, VI and Vd to be compared to a capacitor voltage level (Vsc).

17. The pacemaker of claim 16, further comprising:

a capacitor discharge switch;

a bypass capacitor connected across the battery power terminal; and

means to provide a brown out voltage limit;

wherein the CTM control circuitry is adapted to compare;

Vd to Vsc to limit the discharge of the capacitor and open the capacitor discharge switch;

VI to Vsc to begin a time charge measurement after the bypass capacitor (Cb) is discharged and a battery terminal voltage (Vbatt) is driven to the brownout voltage (Vstop) limit; and

VF to Vsc to end the time charge measurement.

18. The pacemaker of claim 9, wherein the VF is programmable by a physician.

19. A pacemaker, including:

a battery power terminal for a pacemaker battery;

a pacing supply storage (PSS) capacitor;

pacemaker control circuitry, including;

a switch capacitor power supply having an input connected to the battery terminal, an output connected to the PSS capacitor, and a clock input to enable the switch capacitor power supply to charge the PSS capacitor;

a clock signal line, a Vstop reference potential line, and a selectable reference potential (Vx) line;

a first comparator having a first input electrically connected to the battery power terminal, a second input connected to the Vstop reference potential line; and

an output;

a second comparator having a first input connected to the selectable reference potential line, a second input connected to the output of the switch capacitor power supply, and an output; and

at least one logic gate, including a first input connected to the output from the first comparator, a second input connected to the output from the second comparator, a third input connected to the clock signal line, and an output connected to the clock input of the switch capacitor power supply;

a discharge switch connected to the PSS capacitor;

sensing and pace control circuitry connected to the battery power terminal; and

charge time measurement (CTM) control circuitry, including;

a number of registers to hold a Vd value corresponding to a desired discharge voltage for the PSS capacitor, a VI value corresponding to an initial voltage across the PSS capacitor to begin a time charge measurement, and a VF value corresponding to a final voltage across the PSS capacitor to end the time charge measurement;

a multiplexer having an output, the multiplexer being operably connected to the number of registers to selectively pass one of the Vd, VI and VF values to the output of the multiplexer;

a D/A converter connected to the output of the multiplexer to convert the selected one of the Vd, VI and VF values to a potential on the selectable reference potential (Vx) line for comparison to the output of the switch capacitor power supply by the second comparator; and

a control circuit connected to the multiplexer to select one of the Vd, VI and VF values to appropriately control the switch capacitor power supply to charge the PSS capacitor from the discharge voltage to the initial voltage and from the initial voltage to the final voltage, the control circuit being connected to the discharge switch to selectively discharge the PSS capacitor from the final voltage to the desired discharge voltage, the control circuit being connected to the clock signal line, the control circuit including circuitry to determine a rate of charge storage in the PSS capacitor from the initial voltage to the final voltage, and estimate battery depletion based on the rate of charge storage in the PSS capacitor.

20. The pacemaker of claim 19, wherein the control circuit includes circuitry to measure a charge time for the storage capacitor to determine the rate of charge storage, to determine a value for an internal AC impedance for the battery based on the rate of charging, and to estimate the battery depletion using the value for the internal AC impedance.

21. A system, comprising:

a battery power terminal for a battery;

a capacitor electrically connected to the battery power terminal;

means to control current flow from the battery power terminal to charge the capacitor;

means to access a predetermined set of charge time measurement set-up parameters and a predetermined elective replacement time (ERT) charge time limit associated with an AC impedance target for the battery, the predetermined set of charge time measurement set-up parameters including;

a final voltage (VF) to end a charge time measurement for determining the rate of charge storage in the capacitor;

an initial reference voltage (VI) to begin the charge time measurement for determining the rate of charge storage in the capacitor; and

a voltage level (Vd) to which the capacitor is discharged prior to beginning the time measurement for determining the rate of charge storage in the capacitor, Vd being less than VI;

means to determine a rate of charge storage in the capacitor using the predetermined set of charge time measurement set-up parameters;

means to compare the determined rate of charge storage in the capacitor to the predetermined ERT charge time limit for the predetermined set of charge time measurement set-up parameters; and

means to declare an ERT based on a number of comparisons between the determined rate of charge storage in the capacitor and the ERT charge time limit.

22. The system of claim 21, wherein further comprising:

means to calculate an AC impedance of the battery using the determined rate of charge storage and the predetermined set of charge time measurement set-up parameters; and

means to determine the ERT charge time limit using the AC impedance of the battery.

23. The system of claim 21, further comprising:

a table containing relationships between a number of AC impedances for the battery and a number of rates of charge storage;

means to perform a table look-up using the table and the determined rate of charge storage to determine the AC impedance of the battery; and

means to determine the ERT charge time limit using the AC impedances.

24. The system of claim 21, further comprising means to display charge remaining in the battery.

25. The system of claim 24, wherein the programmer circuitry includes means to graphically display the charge remaining in the battery.

26. The system of claim 21, further comprising means to estimate a time until the ERT is declared.