Sense-amp based adder with source follower evaluation tree

• US 20040073592A1
• Filed: 06/10/2002
• Published: 04/15/2004
• Est. Priority Date: 06/10/2002
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Kim, Jae-Joon, Joshi, Rajiv V., Chuang, Ching-Te K., Roy, Kaushik
• Granted Patent: US 6,789,099 B2
• Time in Patent Office: Days
• US Class Current: 708/710
• CPC Class Codes: G06F 2207/3872 Precharge of output to prevent leakage
• CPC Class Codes: G06F 2207/4814 Non-logic devices, e.g. operational amplifiers
• CPC Class Codes: G06F 7/503 using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
• CPC Class Codes: G06F 7/507 using selection between two conditionally calculated carry or sum values
• CPC Class Codes: G06F 7/508 using carry look-ahead circuits

Abstract

A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Claims

1. An N-bit two level lookahead adder for adding two N-bit numbers, comprising summing means for calculating alternative partial M-bit sums;

a first set of carry modules for generating g_i, p_i and k_i signals for each of the N bits;

a second set of carry modules, responsive to said g_i, p_i and k_i signals, for generating a set of M-bit G, P and K signals therefrom, each of said set of carry modules having a sense amplifier connected to a logic evaluation module containing two connecting nodes connected to said sense amplifier, and a chain of source follower transistors having a first node, a final node and a set of intermediate nodes controllably connected to both said two connecting nodes by first and second sets of connecting transistors,

first precharge means for precharging each of said set of two connecting nodes to ground;

means for charging said first node to a reference voltage other than ground in an evaluation mode; and

a set of output modules, responsive to said set of carry signals, for selecting alternative partial sums and connecting a selected set of said alternative partial sums to a set of output terminals.

2. An adder according to claim 1, comprising a set of partially depleted silicon transistors disposed in an integrated circuit formed in a device layer disposed above an insulating layer on a substrate.

3. An adder according to claim 2, in which said set of partially depleted transistors have floating bodies.

4. An adder according to claim 1, further comprising a global carry module for generating carry signals comprising first and second carry logic modules, each comprising a chain of source follower transistors connected through a series of intermediate nodes, each of said intermediate nodes being connected to ground and to a reference voltage through transistors controlled by said G and K signals, each of said intermediate nodes of said first and second carry logic modules being connected to corresponding first and second inputs of a set of sense amplifiers, the outputs of said set of sense amplifiers being said carry signals.

5. An adder according to claim 4, comprising a set of partially depleted silicon transistors disposed in an integrated circuit formed in a device layer disposed above an insulating layer on a substrate.

6. An adder according to claim 5, in which said set of partially depleted transistors have floating bodies.