Fast-path apparatus for receiving data corresponding a TCP connection

• US 20040073703A1
• Filed: 09/27/2002
• Published: 04/15/2004
• Est. Priority Date: 10/14/1997
• Status: Active Grant

• Current Assignee: Alacritech, Inc.
• Original Assignee: Alacritech, Inc.
• Inventors: Higgen, David A., Philbrick, Clive M., Boucher, Laurence B., Craft, Peter K., Blightman, Stephen E. J., Starr, Daryl D.
• Granted Patent: US 7,237,036 B2
• Time in Patent Office: Days
• US Class Current: 709/245
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 69/12 Protocol engines
• CPC Class Codes: H04L 69/16 Implementation or adaptation of Internet protocol [IP], of transmission control protocol [TCP] or of user datagram protocol [UDP]
• CPC Class Codes: H04L 69/161 Implementation details of TCP/IP or UDP/IP stack architecture; Specification of modified or new header fields
• CPC Class Codes: H04L 69/22 Parsing or analysis of headers

Abstract

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

Claims

1. A device for use with a first apparatus that is connectable to a second apparatus by a network, the first apparatus containing a memory and a first processor operating a stack of protocol processing layers that create a context for communication between an application of the first apparatus and an application of the second apparatus, the device comprising:

a communication processing mechanism connected to the first processor and to the network, said communication processing mechanism containing a second processor and instructions to choose, by referencing the context, whether a network message packet is processed by the protocol processing layers or the context is employed to transfer data contained in said packet between the network and the first apparatus memory.

2. The device of claim 1, wherein said communication processing mechanism includes a receive sequencer with directions to classify said packet, wherein said packet contains control information corresponding to the stack of protocol layers.

3. The device of claim 1, wherein said communication processing mechanism includes a receive sequencer with directions to generate a summary of a message packet received from the network, said packet containing control information corresponding to the stack of protocol layers, and said instructions including an instruction to compare said summary with said context.

4. The device of claim 1, wherein said instructions include a first instruction to create a header corresponding to said context and having control information corresponding to several of the protocol processing layers, and said instructions include a second instruction to prepend said header to said data for transmission of said packet from the first apparatus to the second apparatus.

5. The device of claim 1, wherein said communication processing mechanism has a direct memory access unit to send, based upon said context, said data from said communication processing mechanism to the first apparatus memory, without a header accompanying said data.

6. The device of claim 1, wherein said instructions include receive instructions to process packets received by the first apparatus from the network and transmit instructions to process packets transmitted from the first apparatus to the network.

7. The device of claim 1, wherein said context includes Internet Protocol (IP) addresses of said first and said second apparatuses and Transport Control Protocol (TCP) ports of said first and said second apparatuses.

8. The device of claim 1, wherein said communication processing mechanism includes a queue manager connected to said second processor.

9. A device for use with a first apparatus that can communicate with a second apparatus by a network, the first apparatus containing a first processor operating a stack of protocol processing layers that create a Transport Control Protocol (TCP) connection between the first apparatus and the second apparatus, the device comprising:

a receive mechanism coupled to the network and having logic to classify a message packet received from the network by the device, said message packet containing data and a header with control information corresponding to several of said protocol layers, said logic including directions to create a descriptor of said packet, and

a second processor coupled to said receive mechanism and to the first apparatus, having instructions to compare said descriptor with the connection and to choose, based upon said comparing, whether to send said message packet to the stack for protocol processing or to send said data directly to a destination in the first apparatus without processing said message packet by the stack.

10. The device of claim 9, wherein said receive mechanism includes a sequencer.

11. The device of claim 9, further comprising a queue manager containing logic circuits to provide information for said second processor.

12. The device of claim 9, wherein said receive mechanism and said second processor process a plurality of message packets to send data from each of said packets to said destination without an interrupt.

13. The device of claim 9, wherein the connection is one of a plurality of TCP connections maintained by the device, and a hash of each said connection is stored in a memory of the device.

14. The device of claim 13, further comprising a least recently used register (LRU) for determining which of said connections are stored in said memory.

15. The device of claim 9, wherein said receive mechanism has a sequence of hardware logic units for processing said header.

16. The device of claim 9, further comprising a direct memory access (DMA) controller for sending, based upon said connection, said data to said destination without said header.

17. The device of claim 9, further comprising directions for said second processor to transmit a second message packet from the first apparatus to the network without employing the stack, including directions to create a header corresponding to said connection as part of said second message packet.

18. A device for processing communication between a network and a host having a stack of protocol layers, said device comprising:

a sequencer that categorizes a message packet received from the network to create a summary of said packet, said packet including data and a header containing information corresponding to a transport layer protocol,

a memory to store said packet and said summary,

a microprocessor to match said summary with a connection context and to move said data without said information to a destination in the host indicated by said context.

19. The device of claim 18, wherein said microprocessor includes a plurality of pipelined processors, with one of said processors configured to transmit network messages and another of said processors configured to receive network messages.

20. The device of claim 18, further comprising a CPU operating a stack of protocol processing layers to process a second packet having a second summary that does not match said connection context.

21. A device for transferring a message between a network and a host computer, wherein the message includes a packet having a series of headers corresponding to a sequence of protocol layers, the device comprising a sequencer that parses the series of headers as a stream of bits to generate a status of said packet, and a processor including logic to process a Transport Control Protocol (TCP) header of said packet.

22. The device of claim 21, further comprising a central processing unit (CPU) running a protocol processing stack to generate a Transmission Control Block (TCB) corresponding to said packet.