Method and system of managing virtualized physical memory in a memory controller and processor system

• US 20040073765A1
• Filed: 10/10/2002
• Published: 04/15/2004
• Est. Priority Date: 10/10/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ghai, Sanjeev, Arimilli, Ravi Kumar, Wright, Kenneth Lee, Dodson, John Steven
• Granted Patent: US 6,907,494 B2
• Time in Patent Office: Days
• US Class Current: 711/202
• CPC Class Codes: G06F 12/0653 with centralised address assignment
• CPC Class Codes: G06F 2212/657 Virtual address space management

Abstract

A processor contains a move engine and a memory controller contains a mapping engine that, together, transparently reconfigure physical memory to accomplish addition, subtraction, or replacement of a memory module. A mapping engine register stores current and new real addresses that enable the engines to virtualize the physical address of the memory module being reconfigured and provide the reconfiguration in real-time through the use of hardware functionality and not software. Using the current and new real addresses to select a source and a target, the move engine copies the contents of the memory module to be removed or reconfigured into the remaining or inserted memory modules. Then, the real address associated with the reconfigured memory module is re-assigned to the memory module receiving the copied contents, thereby creating a virtualized physical mapping from the addressable real address space being utilized by the operating system into a virtual physical address space. During the process of moving the memory contents, the mapping engine responds to Write memory requests addressed to either the current or new real address space. As will be appreciated, a memory module can be inserted, removed or replaced in physical memory without the operating system having to direct and control the reconfiguration of physical memory to accomplish the physical memory change.

Claims

1. A method of data processing within a data processing system, wherein the data processing system including a processor device for generating memory accesses containing physical addresses associated with memory locations of a physical memory system for reading and writing of data thereto, the physical memory system including a plurality of memory controllers, each responding to memory accesses requested by the processor by writing and reading memory blocks stored within one or more memory modules coupled thereto, the method comprising:

setting a register in each of a first and a second memory controller of the plurality of controllers that are to be reconfigured, wherein a first and a second memory module is coupled to the first and second memory controller, respectively, each register being set to indicate a current real address and a new real address for the coupled memory module, and wherein the first and second memory controllers each respond to memory accesses addressed to the current real address stored in their respective registers;

copying the plurality of memory blocks from the first memory module to the second memory module based on the current real addresses of the first and second memory modules; and

after completing the copying step, configuring the first and second memory controllers to respond only to memory accesses addressed to the new real address stored in their respective registers.

2. The method of claim 1, wherein, during the copying step, each memory controller of the plurality of memory controllers responds to a write memory request addressed to either the current real address or the new real address stored in the memory controller'"'"'s register.

3. The method of claim 1, wherein the first memory module is removed from the memory system following the configuring step, the current real address for the first memory module is within a current addressable space for the physical memory system, and the new real address for the first memory module is outside a current addressable space for the physical memory system.

4. The method of claim 1, wherein the first memory module is inserted into the memory system prior to the copying step and wherein the current real address for the first memory module is within a current addressable space for the physical memory system and the new real address for the second memory module is outside a current addressable space for the physical memory system.

5. The method of claim 1, the method further comprising notifying the processor that a configuration of the plurality of memory modules is being modified, and wherein the setting step is performed in response to the notification.

6. The method of claim 1, wherein, during the copying step, each memory controller of the plurality of memory controllers responds to a read memory access addressed to only the current real address stored in the memory controller'"'"'s register.

7. A system having a processor device for generating memory accesses containing real addresses associated with memory locations of a physical memory system for reading and writing of data thereto, and a plurality of memory modules in the physical memory system for storing the data as a plurality of memory blocks, each memory block comprising contiguous bytes of physical memory, the system comprising:

a plurality of memory controllers, wherein each memory controller of the plurality of memory controllers has one or more memory modules of the plurality of memory modules coupled thereto, and wherein each memory controller of the plurality of memory controllers responds to memory accesses by writing and reading memory blocks stored within the one or more of the memory modules coupled thereto;

a first register within a first memory controller of the plurality of memory controllers having a first field storing a current real address corresponding to a first memory module of the plurality of memory modules coupled thereto and a second field storing a new real address corresponding to the first memory module;

a second register within a second memory controller of the plurality of memory controllers having a first field storing a current real address corresponding to a second memory module of the plurality of memory modules coupled thereto and a second field storing a new real address corresponding to the second memory module;

a move engine that, in response to a notification that a configuration of the first and second memory modules is being modified, copies the plurality of memory blocks from the first memory module to the second memory module based on the current real addresses of the first and second memory modules;

a first mapping engine within the first memory controller that enables the first memory controller to respond to memory accesses addressed to the current real address stored in the first register during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module and that enables the first memory controller to only respond to memory accesses addressed to the new real address stored in the first register after the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module; and

a second mapping engine within the second memory controller that enables the second memory controller to respond to memory accesses addressed to the current real address stored in the second register during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module and that enables the second memory controller to only respond to memory accesses addressed to the new real address stored in the second register after the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

8. The system of claim 7, wherein the first and second mapping engines enable their respective memory controllers to respond to write memory accesses addressed to either the current real address or the new real address stored in their respective registers during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

9. The system of claim 7, wherein the first memory module is removed from the physical memory system after the second mapping engine enables the second memory controller to only respond to memory accesses addressed to the new real address stored in the second register after the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

10. The method of claim 9, wherein the new real address stored in the second register is equivalent to the current real address stored in the first register and the new real address stored in the first register is outside the current addressable space of the physical memory system.

11. The system of claim 7, wherein the second memory module is inserted into the physical memory system before the move engine copies the plurality of memory blocks from the first memory module to the second memory module.

12. The system of claim 11, wherein the new real address stored in the second register is equivalent to the current real address stored in the first register and the new real address stored in the first register is within the current addressable space of the physical memory system.

13. The system of claim 7, wherein the first and second mapping engines enable their respective memory controllers to respond to read memory accesses addressed to only the current real address stored in their respective registers during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

14. A data processing system comprising:

a physical memory system having a plurality of memory modules for storing data as a plurality of memory blocks, each memory block comprising contiguous bytes of physical memory;

a plurality of processor devices for generating memory accesses containing real addresses associated with memory locations of the physical memory system for reading and writing of data thereto;

a plurality of memory controllers, wherein each memory controller of the plurality of memory controllers has one or more memory modules of the plurality of memory modules coupled thereto, and wherein each memory controller of the plurality of memory controllers responds to memory accesses by writing and reading memory blocks stored within the one or more of the memory modules coupled thereto;

a first register within a first memory controller of the plurality of memory controllers having a first field storing a current real address corresponding to a first memory module of the plurality of memory modules coupled thereto and a second field storing a new real address corresponding to the first memory module;

a second register within a second memory controller of the plurality of memory controllers having a first field storing a current real address corresponding to a second memory module of the plurality of memory modules coupled thereto and a second field storing a new real address corresponding to the second memory module;

a move engine that, in response to a notification that a configuration of the first and second memory modules is being modified, copies the plurality of memory blocks from the first memory module to the second memory module based on the current real addresses of the first and second memory modules;

a first mapping engine within the first memory controller that enables the first memory controller to respond to memory accesses addressed to the current real address stored in the first register during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module and that enables the first memory controller to respond to memory accesses addressed to the new real address stored in the first register after the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module; and

a second mapping engine within the second memory controller that enables the second memory controller to respond to memory accesses addressed to the current real address stored in the second register during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module and that enables the second memory controller to respond to memory accesses addressed to the new real address stored in the second register after the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

15. The system of claim 14, wherein the first and second mapping engines enable their respective memory controllers to respond to write memory accesses addressed to either the current real address or the new real address stored in their respective registers during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

16. The system of claim 14, wherein the first memory module is removed from the physical memory system after the second mapping engine enables the second memory controller to only respond to memory accesses addressed to the new real address stored in the second register after the time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.

17. The method of claim 16, wherein the new real address stored in the second register is equivalent to the current real address stored in the first register and the new real address stored in the first register is outside the current addressable space of the physical memory system.

18. The system of claim 14, wherein the second memory module is inserted into the physical memory system before the move engine copies the plurality of memory blocks from the first memory module to the second memory module.

19. The system of claim 18, wherein the new real address stored in the second register is equivalent to the current real address stored in the first register and the new real address stored in the first register is within the current addressable space of the physical memory system.

20. The system of claim 14, wherein the first and second mapping engines enable their respective memory controllers to respond to read memory accesses addressed to only the current real address stored in their respective registers during a time period that the move engine is copying the plurality of memory blocks from the first memory module to the second memory module.