Fail-over of multiple memory blocks in multiple memory modules in computer system

• US 20040073829A1
• Filed: 12/16/2002
• Published: 04/15/2004
• Est. Priority Date: 07/16/1998
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Olarig, Sompong P.
• Granted Patent: US 7,055,054 B2
• Time in Patent Office: Days
• US Class Current: 714/6
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

A computer system has a memory controller for controlling accesses to multiple memory modules, each having multiple memory blocks, and a fail-over circuit for failing-over individual memory blocks from multiple memory modules. The digital information stored in an individual memory block that has experienced memory errors in excess of a permissible threshold is copied to an auxiliary memory location. The memory accesses directed to the failed-over memory block are intercepted and redirected to the auxiliary memory location. Tags are stored to identify failed-over memory modules and corresponding auxiliary memory modules, so a tag look-up for an accessed memory address can generate a hit signal when the memory access is to a failed-over memory module and cause the auxiliary memory module to respond to the memory access.

Claims

1. A computer system comprising:

a bus subsystem for transferring digital information;

a processing unit for processing the digital information;

a memory module array having multiple memory modules, each of the memory modules having multiple memory blocks for storing the digital information; and

a memory fail-over subsystem cooperatively coupled to fail-over individual memory blocks, and the digital information stored therein, of one or more of the memory modules,

wherein the memory fail-over subsystem fails-over an individual memory block when a data error for the individual memory block exceeds a permissible threshold, and accesses to remaining memory blocks in the same memory module as the failed-over memory block are satisfied by the remaining memory blocks in the same memory module.

2. The computer system of claim 1, further comprising an auxiliary memory cooperatively coupled to receive the digital information intended for failed-over memory blocks, wherein accesses to individual failed-over memory blocks are satisfied by the auxiliary memory.

3. The computer system of claim 2, further comprising a tag storage having storage locations for storing tags identifying one or more failed-over memory blocks in one or more of the memory modules and pointing to a location in the auxiliary memory where the digital information intended for the failed-over memory blocks is stored.

4. The computer system of claim 3, further comprising:

a memory controller for controlling transfer, between the bus subsystem, the processing unit and the memory module array, of the digital information; and

a tag look-up circuitry cooperatively coupled to the tag storage to determine whether an access to a memory block is to a failed-over memory block and cooperatively coupled to the memory controller to provide a hit signal thereto if the access is to a failed-over memory block.

5. The computer system of claim 1, further comprising:

a tag storage having storage locations for storing tags corresponding to one or more memory blocks in one or more of the memory modules;

wherein a tag corresponding to a failed-over memory block is stored in the tag storage upon fail-over of the failed-over memory block.

6. The computer system of claim 6, further comprising:

a memory controller for controlling transfer, between the bus subsystem, the processing unit and the memory module array, of the digital information; and

an auxiliary memory cooperatively coupled to the memory controller to respond to memory accesses,

wherein the digital information stored in a failed-over memory block in a memory module is transferred to an auxiliary location in the auxiliary memory, and

wherein the tag corresponding to the failed-over memory block further corresponds to the auxiliary location for the transferred digital information.

7. A memory controller for controlling functions of multiple memory modules, each having multiple memory blocks, comprising:

a fail-over circuitry for failing-over individual memory blocks in one or more of the memory modules;

wherein the memory fail-over subsystem fails-over an individual memory block when a data error for the individual memory block exceeds a permissible threshold, and accesses to the non-failed-over memory blocks are satisfied by the memory blocks in the memory modules.

8. The memory controller of claim 7, further comprising an auxiliary memory cooperatively coupled to receive digital information intended for failed-over memory blocks, wherein accesses to individual failed-over memory blocks are satisfied by the auxiliary memory.

9. The memory controller of claim 8, further comprising a tag storage having storage locations for storing tags identifying one or more failed-over memory blocks in one or more of the memory modules and pointing to a location in the auxiliary memory where the digital information intended for the failed-over memory blocks is stored.

10. The memory controller of claim 7, further comprising:

a tag storage having storage locations for storing tags corresponding to one or more memory blocks in one or more of the memory modules,

wherein a tag corresponding to a failed-over memory block is stored in the tag storage upon fail-over of the memory block.

11. The memory controller of claim 10, further comprising:

an auxiliary memory capable of responding to memory accesses;

wherein the digital information stored in a failed-over memory block in a memory module is transferred to an auxiliary location in the auxiliary memory, and

wherein the tag corresponding to the failed-over memory block further corresponds to the auxiliary location for the transferred digital information.

12. The memory controller of claim 11, further comprising a tag look-up circuitry cooperatively coupled to the tag storage to determine whether an access to a memory block is to a failed-over memory block, and providing a hit signal if the access is to a failed-over memory block, wherein the tag look-up circuitry identifies a tag corresponding to the failed-over memory block, and the memory block access is satisfied by the auxiliary location corresponding to the identified tag.

13. A method of controlling accesses to multiple memory modules, each having multiple memory blocks, comprising:

upon detection of errors for a particular memory block exceeding a permissible error threshold, failing-over only the particular memory block;

satisfying accesses to non-failed-over memory blocks by the memory blocks in the memory modules.

14. The method of claim 13, further comprising:

detecting an access to a failed-over memory block; and

satisfying the access to the failed-over memory block from an auxiliary memory block.

15. The method of claim 13, further comprising:

performing a tag look-up to determine whether a memory block access is to a failed-over memory block.

16. The method of claim 15, wherein the looked-up tag indicates a corresponding auxiliary memory block, further comprising:

confirming that digital information stored in the corresponding auxiliary memory block to the looked-up tag is valid.

17. The method of claim 15, wherein the looked-up tag indicates a corresponding auxiliary memory block, further comprising:

sending a hit signal indicating that the access to the failed-over memory block will be satisfied by the corresponding auxiliary memory block.

18. The method of claim 15, wherein the looked-up tag indicates a corresponding auxiliary memory block, further comprising:

accessing the corresponding auxiliary memory block indicated by the looked-up tag.

19. The method of claim 15, wherein the looked-up tag indicates a corresponding auxiliary memory block, further comprising:

satisfying the access to the failed-over memory block from the corresponding auxiliary memory block.

20. The method of claim 13, further comprising:

storing a tag value corresponding to the failed-over memory block.

21. The method of claim 20, further comprising:

transferring digital information from the failed-over memory block to the auxiliary memory block.

22. The method of claim 21, further comprising:

correlating the tag value with an auxiliary memory block.

23. The method of claim 20, further comprising:

setting a valid flag for the tag value.

24. The method of claim 13, further comprising:

transferring digital information stored in the failed-over memory block to an auxiliary memory location.

25. A memory controller comprising:

a plurality of means for storing digital information, each of the means for storing digital information having multiple submeans; and

means for failing over individual submeans, and the digital information stored therein, of one or more of the means for storing digital information when an error data for the individual submeans exceeds a permissible threshold, and accesses to remaining submeans in the same means for storing digital information as the failed-over submeans are satisfied by the remaining submeans in the same means for storing digital information.

26. The memory controller of claim 25, further comprising an auxiliary storage means for satisfying accesses to individual failed-over submeans, and for receiving digital information intended for failed-over submeans.

27. The memory controller of claim 26, further comprising a tag storage means for storing tags identifying one or more failed-over submeans in one or more of the means for storing digital information and pointing to a location in the auxiliary storage means where the digital information intended for the failed-over submeans is stored.

28. The memory controller of claim 25, further comprising:

a tag storage means for storing tags corresponding to one or more failed-over submeans in one or more of the means for storing digital information;

29. The memory controller of claim 25, further comprising:

a tag storage means for storing tags corresponding to one or more failed-over submeans in one or more of the means for storing digital information;

an auxiliary storage means for storing digital information stored in a failed-over submeans,

wherein the tag corresponding to the failed-over submeans further corresponds to an auxiliary location for the stored digital information in the auxiliary storage means.

30. The memory controller of claim 28, further comprising:

a tag look-up means for determining whether an access to a submeans is to a failed-over submeans by identifying a tag stored in the tag storage means and for providing a hit signal if the access is to a failed-over submeans;

means for satisfying the access to the submeans by the auxiliary location corresponding to the identified tag.