CIRCUIT FOR PRESERVING DATA IN A FLIP-FLOP AND A METHOD OF USE

• US 20040075478A1
• Filed: 10/16/2002
• Published: 04/22/2004
• Est. Priority Date: 10/16/2002
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Correale, Anthony Jr., Goodall, William James III
• Granted Patent: US 6,762,638 B2
• Time in Patent Office: Days
• US Class Current: 327/202
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors

Abstract

A method and a flip-flop is disclosed in which power consumption is reduced in a standby mode. In a first aspect, the flip-flop comprises a first latch adapted to be coupled to a first power supply and a second latch coupled to the first latch and adapted to be coupled to a second power supply. The first and second power supplies are independently controllable to minimize power consumption in a standby mode. In a second aspect, a method for minimizing the power consumption of a flip-flop is also disclosed. The flip-flop includes a first latch and a second latch coupled thereto. The method comprises providing a first independently controllable power supply coupled to the master latch; and providing a second independently controllable power supply coupled to the slave latch. The method further includes reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode.

Claims

1. A flip-flop comprising:

a first latch adapted to be coupled to a first power supply; and

a second latch coupled to the first latch and adapted to be coupled to a second power supply, wherein the first and second power supplies are independently controllable to minimize power consumption when the flip-flop is in a power saving mode.

2. The flip-flop of claim 1 wherein, in a power saving mode, the voltage of at least one of the first and second power supplies is reduced.

3. The flip-flop of claim 1 wherein, in a power saving mode, the voltage of the power supply coupled to the latch which contains contents to be preserved is reduced to a voltage to preserve the state of the contents and the other power supply is reduced to substantially zero volts.

4. The flip-flop of claim 1 wherein the first latch is a master latch.

5. The flip-flop of claim 1 wherein the second latch is a slave latch.

6. The flip-flop of claim 1 further comprising a first clock coupled to the first latch and a second clock coupled to the second latch.

7. The flip-flop of claim 6 wherein the first clock and the second clock are free running.

8. The flip-flop of claim 6 wherein the first clock is gated and the second clock is free running.

9. The flip-flop of claim 6 wherein the first clock is free running and the second clock is gated.

10. The flip-flop of claim 6 wherein the first clock is gated and the second clock is gated.

18. The flip-flop of claim 1 wherein, in a power saving mode, the voltage of at least one of the first and second power supplies is reduced.

19. The flip-flop of claim 1 wherein, in a power saving mode, the voltage of the power supply coupled to the latch which contains contents to be preserved is reduced to a voltage to preserve the state of the contents and the other power supply is reduced to substantially zero volts.

11. A flip-flop comprising:

a first latch adapted to be coupled to a first power supply, the first latch for receiving at least one bit;

a second latch coupled to the first latch and adapted to be coupled to a second power supply, the second latch for storing the at least one bit from the first latch, wherein the size of the second latch is minimized to reduce power consumption; and

a multiplexor coupled to the first latch and to the second latch for outputting the at least one bit from the first latch when a clock to the multiplexor is active and for outputting the at least one bit from the second latch when the clock is inactive, wherein the first and second power supplies are independently controllable.

12. The flip-flop of claim 11, wherein the multiplexor is a shunt multiplexor.

13. The flip-flop of claim 11 wherein a first clock causes the at least one bit to be provided to the first latch.

14. The flip-flop of claim 11 wherein the first latch is a master latch.

15. The flip-flop of claim 14 wherein the second latch is a slave latch.

16. The flip-flop of claim 15 which includes a restore mechanism which multiplexes the data and an output of the slave latch to enable recovery of the state of the contents of the master latch.

17. The flip-flop of claim 15 which includes a state saving latch which is coupled to the second power supply and is only activated upon detection of standby power saving mode.

20. A flip-flop comprising:

a master latch adapted to be coupled to a first power supply, the master latch for receiving at least one bit; and

a slave latch coupled to the master latch and adapted to a second power supply, the slave latch for storing the at least one bit from the master latch wherein the size of the latch is minimized to reduce power consumption; and

a shunt multiplexor coupled to the master latch and to the slave latch for outputting the at least one bit from the master latch when a clock to the multiplexor is active and for outputting the at least one bit from the slave latch when the clock is inactive, the voltage of the power supply coupled to the latch which contains contents to be preserved is reduced to a voltage to preserve the state of the contents and the other power supply is reduced to substantially zero volts.

21. The flip-flop of claim 20 which includes a restore mechanism which multiplexes the data and an output of the slave latch to enable recovery of the state of the contents of the master latch.

22. The flip-flop of claim 20 which includes a state saving latch which is coupled to the second power supply and is only activated upon detection of standby power saving mode.

23. A flip-flop comprising:

a master latch adapted to be coupled to a first power supply, the master latch for receiving at least one bit; and

a slave latch coupled to the master latch and adapted to a second power supply, the slave latch for storing the at least one bit from the master latch wherein the size of the latch is minimized to reduce power consumption;

a shunt multiplexor coupled to the master latch and to the slave latch for computing the at least one bit from the master latch when a clock to the multiplexor is active and for outputting the at least one bit from the slave latch when the clock is inactive, the voltage of the power supply coupled to the latch which contains contents to be preserved is reduced to a voltage to preserve the state of the contents and the other power supply is reduced to substantially zero volts;

a restore mechanism which multiplexes the data and an output of the slave latch to enable recovery of the state of the contents of the master latch; and

a state saving latch which is coupled to the second power supply and is only activated upon detection of the power saving mode.

24. A method for minimizing the power consumption of a flip-flop, the flip-flop including a first latch and a second latch coupled thereto;

the method comprising the steps of;

(a) providing a first independently controllable power supply coupled to the first latch;

(b) providing a second independently controllable power supply coupled to the second latch; and

(c) reducing the voltage of at least one of the first and second power supplies responsive to the detection of a power saving mode.

25. The method of claim 24 wherein, in a power saving mode, the voltage of the power supply coupled to the latch which contains contents to be preserved is reduced to a voltage to preserve the state of the contents and the other power supply is reduced to substantially zero volts.

26. The method of claim 24 wherein the first latch is a master latch.

27. The method of claim 26 wherein the second latch is a slave latch.

28. The method of claim 27 further comprising a first clock coupled to the first latch and a second clock coupled to the second latch.

29. A method for returning normal mode from power saving mode to preserve the contents in a flip-flop, the flip-flop including a first latch and a second latch coupled thereto, the method comprising the steps of:

(a) providing a first independently controllable power supply coupled to the master latch;

(b) providing a second independently controlling power supply coupled to the second latch, wherein the at least one of the first and second power supplies is at substantially zero volts and the other of the first and second power supplies is at a reduced voltage such that the state of the contents in the associated latch is preserved;

(c) detecting the normal mode; and

(d) restoring the first and second power supplies to full values.