Array substrate having polysilicon TFT for liquid crystal display device and method of manufacturing the same

• US 20040075781A1
• Filed: 05/28/2003
• Published: 04/22/2004
• Est. Priority Date: 10/16/2002
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Sohn, Choong-Yong
• Granted Patent: US 6,842,202 B2
• Time in Patent Office: Days
• US Class Current: 349/43
• CPC Class Codes: G02F 1/136259 Repairing; Defects
• CPC Class Codes: G02F 1/136268 Switch defects
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line

Abstract

An array substrate for a liquid crystal display (LCD) device includes a plurality of gate lines extending along a first direction on a first substrate, a plurality of data lines extending along a second direction on the first substrate, the gate and data lines defining a pixel region by crossing each other, a thin film transistor formed at a portion adjacent to a cross point of the gate and data lines, the thin film transistor having a gate electrode, an active layer, a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode, the source and drain electrodes contacting the active layer via source and drain contact holes, wherein a first portion of the active layer corresponding to the source electrode has an area wider than other portions of the active layer corresponding to the gate electrode and the drain electrode to include areas of the source electrode and the source contact hole, and a pixel electrode in the pixel region, the pixel electrode being electrically connected to the drain electrode.

Claims

1. An array substrate for a liquid crystal display (LCD) device, comprising:

a plurality of gate lines extending along a first direction on a first substrate;

a plurality of data lines extending along a second direction on the first substrate, the gate and data lines defining a pixel region by crossing each other;

a thin film transistor formed at a portion adjacent to a cross point of the gate and data lines, the thin film transistor having a gate electrode, an active layer, a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode, the source and drain electrodes contacting the active layer via source and drain contact holes, wherein a first portion of the active layer corresponding to the source electrode has an area wider than other portions of the active layer corresponding to the gate electrode and the drain electrode to include areas of the source electrode and the source contact hole; and

a pixel electrode in the pixel region, the pixel electrode being electrically connected to the drain electrode.

2. The array substrate according to claim 1, wherein the gate electrode includes a first gate portion that projects from the gate line and extends along the second direction, and a second gate portion that extends along the first direction.

3. The array substrate according to claim 1, wherein the active layer includes polycrystalline silicon.

4. The array substrate according to claim 3, wherein the active layer is L-shaped.

5. The array substrate according to claim 3, wherein the first portion of the active layer corresponding to the source electrode is pentagon-shaped having an apex positioned toward the gate electrode along the first direction.

6. The array substrate according to claim 3, wherein the first portion of the active layer corresponding to the source electrode is triangular-shaped having an apex positioned toward the gate electrode along the first direction.

7. A method for manufacturing an array substrate for a liquid crystal display (LCD) device, comprising:

forming a plurality of gate lines extending along a first direction on a first substrate;

forming a plurality of data lines extending along a second direction on the first substrate, the gate and data lines defining a pixel region by crossing each other;

forming a thin film transistor formed at a portion adjacent to a cross point of the gate and data lines, the thin film transistor having a gate electrode, an active layer, a source electrode extending from the data line, and a drain electrode spaced apart from the source electrode, the source and drain electrodes contacting the active layer via source and drain contact holes, wherein a first portion of the active layer corresponding to the source electrode has an area wider than other portions of the active layer corresponding to the gate electrode and the drain electrode to include areas of the source electrode and the source contact hole; and

forming a pixel electrode in the pixel region, the pixel electrode being electrically connected to the drain electrode.

8. The method according to claim 7, wherein the gate electrode includes a first gate portion that projects from the gate line and extends along the second direction, and a second gate portion that extends along the first direction.

9. The method according to claim 7, wherein the active layer includes polycrystalline silicon.

10. The method according to claim 9, wherein the active layer is L-shaped.

11. The method according to claim 9, wherein the first portion of the active layer corresponding to the source electrode is pentagon-shaped having an apex positioned toward the gate electrode along the first direction.

12. The method according to claim 9, wherein the first portion of the active layer corresponding to the source electrode is triangular-shaped having an apex positioned toward the gate electrode along the first direction.

13. A method for manufacturing an array substrate for a liquid crystal display (LCD) device, comprising:

forming an active layer on a substrate;

forming a gate insulating layer on the active layer and on the substrate;

forming a gate electrode and a gate line on the gate insulating layer, the gate electrode disposed over the active layer;

forming an insulating layer on an entire surface of the substrate on which the gate electrode and the gate line are formed;

forming a source contact hole and a first drain contact hole by etching the gate insulating layer and the insulating layer;

forming a data line and source and drain electrodes spaced apart from each other, the source and drain electrodes contacting the active layer respectively via the source contact hole and the first drain contact hole;

forming a passivation layer having a second drain contact hole on the entire surface of the substrate on which the source and drain electrodes are formed; and

forming a pixel electrode in the pixel region, the pixel electrode being electrically connected to the drain electrode via the second drain contact hole,

wherein a first portion of the active layer corresponding to the source electrode has an area wider than other portions of the active layer corresponding to the gate electrode and the drain electrode to include areas of the source electrode and the source contact hole.

14. The method according to claim 13, wherein the gate electrode includes a first gate portion that projects from the gate line along a first direction, and a second gate portion that extends along a second direction perpendicular to the first direction.

15. The method according to claim 13, wherein the active layer includes polycrystalline silicon.

16. The method according to claim 15, wherein the active layer is L-shaped.

17. The method according to claim 15, wherein the first portion of the active layer corresponding to the source electrode is pentagon-shaped having an apex positioned toward the gate electrode along a direction of the gate line.

18. The method according to claim 15, wherein the first portion of the active layer corresponding to the source electrode is triangular-shaped with an apex positioned toward the gate electrode along a direction of the gate line.

19. An array substrate for a liquid crystal display (LCD) device, comprising:

a plurality of gate lines extending along a first direction on a first substrate;

a plurality of data lines extending along a second direction on the first substrate, the gate and data lines defining a pixel region by crossing each other;

a thin film transistor formed at a portion adjacent to a cross point of the gate and data lines, the thin film transistor having first and second gate electrodes, an active layer, a source electrode, and a drain electrode, wherein a first portion of the active layer corresponding to the source electrode is pentagon-shaped having an apex positioned along the second direction; and

a pixel electrode in the pixel region, the pixel electrode being electrically connected to the drain electrode.

20. An array substrate for a liquid crystal display (LCD) device, comprising:

a plurality of gate lines extending along a first direction on a first substrate;

a plurality of data lines extending along a second direction on the first substrate, the gate and data lines defining a pixel region by crossing each other;

a thin film transistor formed at a portion adjacent to a cross point of the gate and data lines, the thin film transistor having first and second gate electrodes, an active layer, a source electrode, and a drain electrode, wherein a first portion of the active layer corresponding to the source electrode is triangular-shaped with an apex positioned along the second direction; and

a pixel electrode in the pixel region, the pixel electrode being electrically connected to the drain electrode.